在 2017-08-09 11:46,Chen-Yu Tsai 写道:
On Tue, Aug 8, 2017 at 2:46 PM,  <icen...@aosc.io> wrote:
在 2017-08-08 12:13,Chen-Yu Tsai 写道:

On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng <icen...@aosc.io> wrote:

Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header

Signed-off-by: Icenowy Zheng <icen...@aosc.io>

Could you provide a reference as to where or how you found out
about this?


I assume you've mapped out what each bit means by testing it?


Toggling bit 0 will make at least 0x0 (CPUS_CFG_REG) inaccessible.
Toggling bit 1 will make at least 0x40 and 0x44 (PLL_CTRL_REG{0,1})
Toggling bit 2 will make at least 0x120 (VDD_SYS_PWR_RST)

(The register names are from http://linux-sunxi.org/PRCM )

Tested-by: Chen-Yu Tsai <w...@csie.org>
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