On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng <icen...@aosc.io> wrote: > Some new Allwinner SoCs' PRCM has a secure switch register, which > controls the access to some clock and power registers in PRCM block. > > Add the definition of this register and its bits in the PRCM header > file. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Could you provide a reference as to where or how you found out about this? Thanks ChenYu _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
