On 08/11/2017 12:25 AM, Ashish Kumar wrote: > The QorIQ LS1088A processor is built on the Layerscape > architecture combining eight ARM A53 processor cores > with advanced, high-performance datapath acceleration > and networks, peripheral interfaces required for > networking, wireless infrastructure, and general-purpose > embedded applications. > > LS1088A is compliant to the Layerscape Chassis Generation 3.
s/compliant to/compliant with/ > > Features summary: > - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs > - Cores are in 2 cluster of 4-cores each > - Cache coherent interconnect (CCI-400) > - One 64-bit DDR4 SDRAM memory controller with ECC > - Data path acceleration architecture 2.0 (DPAA2) > - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs > - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc > > Signed-off-by: Alison Wang <alison.w...@nxp.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com> > Signed-off-by: Ashish Kumar <ashish.ku...@nxp.com> > Signed-off-by: Raghav Dogra <raghav.do...@nxp.com> > Signed-off-by: Shaohui Xie <shaohui....@nxp.com> > --- > > v2: > Fix indentaion in commit msg > Separate RDB and Si specific file > Move Macros to Kconfig > > v3: > 1.Re-based on top of > commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07 > Merge: f0ca30f 6a5691e > Author: Tom Rini <tr...@konsulko.com> > Date: Tue Aug 8 17:06:19 2017 -0400 > > Merge git://git.denx.de/u-boot-x86 > > 2.Incorporate review comments on v2 > Clean up done > > 3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++++++- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 10 ++ > arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 6 +- > arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 > +++++++++++++++++++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 + > arch/arm/dts/fsl-ls1088a.dtsi | 78 +++++++++++++ > arch/arm/include/asm/arch-fsl-layerscape/config.h | 62 +++++++++- > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 + > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 3 +- > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 11 ++ > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 + > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 14 +++ > drivers/ddr/fsl/util.c | 2 +- > drivers/net/ldpaa_eth/Makefile | 1 + > drivers/net/ldpaa_eth/ls1088a.c | 87 ++++++++++++++ > 16 files changed, 447 insertions(+), 9 deletions(-) > create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c > create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi > create mode 100644 drivers/net/ldpaa_eth/ls1088a.c > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > index 1132969..a3c7490 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > @@ -49,6 +49,29 @@ config ARCH_LS1046A > select BOARD_EARLY_INIT_F > imply SCSI > > +config ARCH_LS1088A > + bool > + select ARMV8_SET_SMPEN > + select FSL_LSCH3 > + select SYS_FSL_DDR > + select SYS_FSL_DDR_LE > + select SYS_FSL_DDR_VER_50 > + select SYS_FSL_ERRATUM_A009803 > + select SYS_FSL_ERRATUM_A009942 > + select SYS_FSL_ERRATUM_A010165 > + select SYS_FSL_ERRATUM_A008511 > + select SYS_FSL_ERRATUM_A008850 > + select SYS_FSL_HAS_CCI400 > + select SYS_FSL_HAS_DDR4 > + select SYS_FSL_HAS_SEC > + select SYS_FSL_SEC_COMPAT_5 > + select SYS_FSL_SEC_LE > + select SYS_FSL_SRDS_1 > + select SYS_FSL_SRDS_2 > + select FSL_TZASC_1 > + select ARCH_EARLY_INIT_R > + select BOARD_EARLY_INIT_F > + > config ARCH_LS2080A > bool > select ARMV8_SET_SMPEN > @@ -60,6 +83,7 @@ config ARCH_LS2080A > select SYS_FSL_DDR > select SYS_FSL_DDR_LE > select SYS_FSL_DDR_VER_50 > + select SYS_FSL_HAS_CCN504 > select SYS_FSL_HAS_DP_DDR > select SYS_FSL_HAS_SEC > select SYS_FSL_HAS_DDR4 > @@ -98,7 +122,7 @@ config FSL_LSCH3 > > config FSL_MC_ENET > bool "Management Complex network" > - depends on ARCH_LS2080A > + depends on ARCH_LS2080A || ARCH_LS1088A > default y > select RESV_RAM > help > @@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT > default "fsl,ls1043a-pcie" if ARCH_LS1043A > default "fsl,ls1046a-pcie" if ARCH_LS1046A > default "fsl,ls2080a-pcie" if ARCH_LS2080A > + default "fsl,ls1080a-pcie" if ARCH_LS1088A Did you intentionally use "ls1080a-pcie" here? > help > This compatible is used to find pci controller node in Kernel DT > to complete fixup. > @@ -228,6 +253,7 @@ config MAX_CPUS > default 4 if ARCH_LS1043A > default 4 if ARCH_LS1046A > default 16 if ARCH_LS2080A > + default 8 if ARCH_LS1088A > default 1 > help > Set this number to the maximum number of possible CPUs in the SoC. > @@ -259,14 +285,17 @@ config SYS_CCI400_OFFSET > > config SYS_FSL_IFC_BANK_COUNT > int "Maximum banks of Integrated flash controller" > - depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A > + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A > default 4 if ARCH_LS1043A > default 4 if ARCH_LS1046A > - default 8 if ARCH_LS2080A > + default 8 if ARCH_LS2080A || ARCH_LS1088A > > config SYS_FSL_HAS_CCI400 > bool > > +config SYS_FSL_HAS_CCN504 > + bool > + > config SYS_FSL_HAS_DP_DDR > bool > > @@ -308,6 +337,7 @@ config SYS_FSL_PCLK_DIV > int "Platform clock divider" > default 1 if ARCH_LS1043A > default 1 if ARCH_LS1046A > + default 1 if ARCH_LS1088A > default 2 > help > This is the divider that is used to derive Platform clock from > @@ -401,7 +431,8 @@ config SYS_FSL_ERRATUM_A009929 > config SYS_MC_RSV_MEM_ALIGN > hex "Management Complex reserved memory alignment" > depends on RESV_RAM > - default 0x20000000 > + default 0x20000000 if ARCH_LS2080A > + default 0x70000000 if ARCH_LS1088A That's an odd alignment, isn't it? Are you sure about this? > help > Reserved memory needs to be aligned for MC to use. Default value > is 512MB. > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > index e3ce018..115c3fc 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > @@ -38,3 +38,7 @@ endif > ifneq ($(CONFIG_ARCH_LS1046A),) > obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o > endif > + > +ifneq ($(CONFIG_ARCH_LS1088A),) > +obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o > +endif > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c > index ef97556..13def18 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c > @@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) > return; > } > > +__weak int serdes_get_number(int serdes, int cfg) > +{ > + return cfg; > +} > + What number does this function return? Can you put some comments here, especially you will override it somewhere later? > int is_serdes_configured(enum srds_prtcl device) > { > int ret = 0; > @@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) > printf("invalid SerDes%d\n", sd); > break; > } > + > + cfg = serdes_get_number(sd, cfg); > + > /* Is serdes enabled at all? */ > if (cfg == 0) > return -ENODEV; > @@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 > sd_prctl_mask, > > cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; > cfg >>= sd_prctl_shift; > + > + cfg = serdes_get_number(sd, cfg); > printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); > > if (!is_serdes_prtcl_valid(sd, cfg)) > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > index 3136e3f..d943f84 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S > @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) > switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ > 1: > > -#ifdef CONFIG_FSL_LSCH3 > +#if defined(CONFIG_FSL_LSCH3) && defined (CONFIG_SYS_FSL_HAS_CCN504) With the new CONFIG_SYS_FSL_HAS_CCN504, we don't need to check CONFIG_FSL_LSCH3. The code below is to deal with CCN504. > > /* Set Wuo bit for RN-I 20 */ > #ifdef CONFIG_ARCH_LS2080A > @@ -338,7 +338,9 @@ get_svr: > ldr x1, =FSL_LSCH3_SVR > ldr w0, [x1] > ret > +#endif > > +#ifdef CONFIG_SYS_FSL_HAS_CCN504 > hnf_pstate_poll: > /* x0 has the desired status, return 0 for success, 1 for timeout > * clobber x1, x2, x3, x4, x6, x7 > @@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache) > mov lr, x29 > ret > ENDPROC(__asm_flush_l3_dcache) > -#endif > +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */ > > #ifdef CONFIG_MP > /* Keep literals not used by the secondary boot code outside it */ York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot