> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). > SARADC integer divider control register is 10-bits width. > > Signed-off-by: David Wu <[email protected]> > Acked-by: Philipp Tomsich <[email protected]> > Reviewed-by: Philipp Tomsich <[email protected]> > --- > > Changes in v3: None > Changes in v2: > - Use bitfield_extract > - Use GENMASK > > drivers/clk/rockchip/clk_rk3328.c | 35 ++++++++++++++++++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) >
Applied to u-boot-rockchip, thanks! _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
