> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). > SARADC integer divider control register is 8-bits width. > > Signed-off-by: David Wu <[email protected]> > Acked-by: Philipp Tomsich <[email protected]> > Reviewed-by: Philipp Tomsich <[email protected]> > --- > > Changes in v3: None > Changes in v2: > - Use GENMASK > > arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++ > drivers/clk/rockchip/clk_rk3368.c | 32 > +++++++++++++++++++++++++ > 2 files changed, 37 insertions(+) >
Applied to u-boot-rockchip, thanks! _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
