Hello
Does the code below really work?
On my custom MX6Q board, the code hangs on the read of the
"PCIE_PL_PFLR". Please note that this code sequence is not entered the
first time after a power up; I have to execute a U-Boot reset to
actually trigger the hang. Any ideas what is going wrong?
While debugging it, I also noticed the two problems below.
Tim Harvey wrote:
> + if (is_mx6dq()) {
> + u32 val, gpr1, gpr12;
> +
> + gpr1 = readl(&iomuxc_regs->gpr[1]);
> + gpr12 = readl(&iomuxc_regs->gpr[12]);
> + if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
> + (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
This could be (gpr12 & IOMUXC_GPR12_APPS_LTSSM_ENABLE)) {
> + val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
> + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
> + val |= PCIE_PL_PFLR_FORCE_LINK;
> +
> + imx_pcie_fix_dabt_handler(true);
> + writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
> + imx_pcie_fix_dabt_handler(false);
> +
> + gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
> + writel(val, &iomuxc_regs->gpr[12]);
I think this should be
writel(gpr12, &iomuxc_regs->gpr[12]);
or even better
clrbits_le32(&iomuxc_regs->gpr[12],
IOMUXC_GPR12_APPS_LTSSM_ENABLE);
as in the rest of the file.
Dave
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