> There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, > so we need to double to pll output and then ddr can work > in correct frequency. > > Signed-off-by: Kever Yang <[email protected]> > Acked-by: Philipp Tomsich <[email protected]> > Reviewed-by: Philipp Tomsich <[email protected]> > --- > > Changes in v2: > - update comment for code change > > arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) >
Applied to u-boot-rockchip, thanks! _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
