From: Patrice Chotard <[email protected]> PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR register, available combination are : 00: PLLSAIP = 2 01: PLLSAIP = 4 10: PLLSAIP = 6 11: PLLSAIP = 8
Previously, the divider value was incorrectly set to 6. Signed-off-by: Patrice Chotard <[email protected]> --- drivers/clk/clk_stm32f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 63116e0..51fea8d 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -59,7 +59,7 @@ #define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 -#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17) +#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) -- 1.9.1 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
