On Fri, Jan 19, 2018 at 06:02:40PM +0100, [email protected] wrote: > From: Patrice Chotard <[email protected]> > > PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR > register, available combination are : > 00: PLLSAIP = 2 > 01: PLLSAIP = 4 > 10: PLLSAIP = 6 > 11: PLLSAIP = 8 > > Previously, the divider value was incorrectly set to 6. > > Signed-off-by: Patrice Chotard <[email protected]>
Applied to u-boot/master, thanks! -- Tom
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