Hi
On 1 Feb. 2018 6:06 pm, "Fabio Estevam" <feste...@gmail.com> wrote: [Please do not top post in mailing lists] On Tue, Jan 30, 2018 at 6:40 AM, Mehmet Ali İPİN <mehmet.i...@pavotek.com.tr> wrote: > Dear Estevam, > > I used GPIO 16 to generate the 25MHZ clock, using enable_fec_anatop_clock(1,ENET_25MHZ), in ; > board_eth_init() function, but got 50 MHz on GPIO_16; > > When I manually set the 0x20C_80E0 address(Analog ENET PLL Control Register) 0x8018_2000 on u-boot terminal, I saw 25 MHz on GPIO_16. With > > struct iomuxc *const iomuxc_regs2 = (struct iomuxc *)0x020c80e0; > setbits_le32(&iomuxc_regs2, 0x80182000); > > but still see 50 MHz. I am not sure I follow, sorry. mw.l address value Works but do in the code does not work? Please dump using me Michael > > Are my register write (setbits_le32) function parameters correct? > If correct, in which file and its function Should I set this ENET_PLL_control register? enable_fec_anatop_clock() is the function to configure ENET_PLL. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot