Dear Estevam/Michael,

Thank you very much for your helps/interest.

By trying and error, with these lines of codes, not optimized but now I could 
generate 125 MHZ clock on the GPIO_16 pin,
By using enable_fec_anatop_clock(0,ENET_125MHZ) ;
This clock is applied to the ENET_REF_CLK input of i.mx6, and MAC is also 
generating 25 MHz from RGMII_TxClk pin.

        setbits_le32(&iomuxc_regs1,0x22); // enable SION bit and set ALT2 mode.
        setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
        imx_iomux_set_gpr_register(5, 9, 1, 1);
        imx_iomux_set_gpr_register(1, 21, 1, 1);
        ret = enable_fec_anatop_clock(0,ENET_125MHZ);

=> mii info
PHY 0x05: OUI = 0x0885, Model = 0x21, Rev = 0x01,  10baseT, HDX
=> mii read 5 0
=> setenv ipadr
=> dhcp

I set the speed to 10 Mbps, loop back mode with mii commands, but always see 
this message sequence.

FEC Waiting for PHY auto negotiation to complete......... TIMEOUT !
Could not initialize PHY FEC
BOOTP broadcast 1
BOOTP broadcast 2

I would be very grateful if you advice me to check any u-boot function, status 
register/pin status etc..

Thanks and best regards.

Mehmet Ali

-----Original Message-----
From: Fabio Estevam [] 
Sent: Thursday, February 1, 2018 8:06 PM
To: Mehmet Ali İPİN <>
Subject: Re: FEC Clock

[Please do not top post in mailing lists]

On Tue, Jan 30, 2018 at 6:40 AM, Mehmet Ali İPİN <> 
> Dear Estevam,
> I used GPIO 16 to generate the 25MHZ clock, using 
> enable_fec_anatop_clock(1,ENET_25MHZ), in ;
> board_eth_init() function, but got 50 MHz on GPIO_16;
> When I manually set the 0x20C_80E0 address(Analog ENET PLL Control 
> Register) 0x8018_2000 on u-boot terminal, I saw 25 MHz on GPIO_16. 
> With
>         struct iomuxc *const iomuxc_regs2 = (struct iomuxc *)0x020c80e0;
>         setbits_le32(&iomuxc_regs2, 0x80182000);
> but still see 50 MHz.

I am not sure I follow, sorry.

> Are my register write (setbits_le32) function parameters correct?
> If correct, in which file and its function Should I set this ENET_PLL_control 
> register?

enable_fec_anatop_clock() is the function to configure ENET_PLL.
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