Ensure the NAND controller reset line is deasserted before use.

Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
---
 board/sunxi/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 8891961dcc..54ac018b80 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -286,6 +286,7 @@ static void nand_clock_setup(void)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
        setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
+       setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
 #ifdef CONFIG_MACH_SUN9I
        setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 #else
-- 
2.14.1

_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Reply via email to