[U-Boot] [PATCH 05/12] net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver

[Janine Hagemann]

This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Based on commit 'fc6d39c39581f3c12c95f166ce95ef8beb2047e8' of mainline
linux kernel

Signed-off-by: Janine Hagemann <j.hagem...@phytec.de>
---
 drivers/net/phy/ti.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index d7ae881..086ea4a 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_CTRL           0x1f
 
 /* Extended Registers */
+#define DP83867_CFG4           0x0031
 #define DP83867_RGMIICTL       0x0032
 #define DP83867_RGMIIDCTL      0x0086
 #define DP83867_IO_MUX_CFG     0x0170
@@ -92,11 +93,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX    0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN    0x1f
 
+/* CFG4 bits */
+#define DP83867_CFG4_PORT_MIRROR_EN            BIT(0)
+
+enum {
+       DP83867_PORT_MIRRORING_KEEP,
+       DP83867_PORT_MIRRORING_EN,
+       DP83867_PORT_MIRRORING_DIS,
+};
+
 struct dp83867_private {
        int rx_id_delay;
        int tx_id_delay;
        int fifo_depth;
        int io_impedance;
+       int port_mirroring;
 };
 
 /**
@@ -165,6 +176,26 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int 
prtad,
        phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
+static int dp83867_config_port_mirroring(struct phy_device *phydev)
+{
+       struct dp83867_private *dp83867 =
+               (struct dp83867_private *)phydev->priv;
+       u16 val;
+
+       val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+                phydev->addr);
+
+       if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
+               val |= DP83867_CFG4_PORT_MIRROR_EN;
+       else
+               val &= ~DP83867_CFG4_PORT_MIRROR_EN;
+
+       phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
+               phydev->addr, val);
+
+       return 0;
+}
+
 #if defined(CONFIG_DM_ETH)
 /**
  * dp83867_data_init - Convenience function for setting PHY specific data
@@ -191,6 +222,12 @@ static int dp83867_of_init(struct phy_device *phydev)
        dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
                                 "ti,tx-internal-delay", -1);
 
+       if (fdtdec_get_bool(fdt, node, "enet-phy-lane-swap"))
+               dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
+
+       if (fdtdec_get_bool(fdt, node, "enet-phy-lane-no-swap"))
+               dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
+
        dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
                                 "ti,fifo-depth", -1);
 
@@ -307,6 +344,9 @@ static int dp83867_config(struct phy_device *phydev)
                }
        }
 
+       if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
+               dp83867_config_port_mirroring(phydev);
+
        genphy_config_aneg(phydev);
        return 0;
 
-- 
2.7.4

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