> -----Original Message----- > From: Michael Trimarchi [mailto:[email protected]] > Sent: 2018年6月21日 4:51 > To: Jagan Teki <[email protected]> > Cc: Stefano Babic <[email protected]>; Peng Fan <[email protected]>; > [email protected]; [email protected] > Subject: [PATCH 3/3] spi: mxc_spi: Fix spi mode communication where clock is > inverted > > During spi initialization logic creates a glitch on the clock and if this is > followed > by the chip select this can be interpretated as clock. Add a delay let the > glitch > out of chip select
I did not see issue. What issue do you see and which platform? Adding a delay here seems hacky which forces all SoC using this driver needs a delay. > > Signed-off-by: Michael Trimarchi <[email protected]> > --- > drivers/spi/mxc_spi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index > 0dccc38..d450f16 > 100644 > --- a/drivers/spi/mxc_spi.c > +++ b/drivers/spi/mxc_spi.c > @@ -387,6 +387,7 @@ static int mxc_spi_claim_bus_internal(struct > mxc_spi_slave *mxcs, int cs) > } > reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); > reg_write(®s->intr, 0); > + udelay(50); > > return 0; > } > -- > 2.7.4 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
