On Tue, Sep 25, 2018 at 2:15 PM Ashish Kumar <[email protected]> wrote: > > Add nxp_fspi driver for NXP FlexSPI controller. > This driver supports both IP Mode read/write and > AHB mode READ. > > It supports Single Bit mode read along with Fast Read cmd support. > Octal bit mode is supported for read. > Multi CS are supported tested until 4. > > Signed-off-by: Suresh Gupta <[email protected]> > Signed-off-by: Yogesh Gaur <[email protected]> > Signed-off-by: Rajat Srivastava <[email protected]> > Signed-off-by: Ashish Kumar <[email protected]> > --- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 + > drivers/spi/Kconfig | 7 + > drivers/spi/Makefile | 1 + > drivers/spi/nxp_fspi.c | 1088 +++++++++++++++++++++ > drivers/spi/nxp_fspi.h | 422 ++++++++ > 5 files changed, 1528 insertions(+) > create mode 100644 drivers/spi/nxp_fspi.c > create mode 100644 drivers/spi/nxp_fspi.h > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > index f2111fadc0..5280d33ec8 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > @@ -317,6 +317,16 @@ config QSPI_AHB_INIT > But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB > bus for those flashes to support the full QSPI flash size. > > +config SYS_FSPI_AHB_INIT > + bool "Initialize the FlexSPI controller for AHB mode" > + depends on NXP_FSPI > + default n > + help > + Initialize the FlexSPI controller for AHB mode and mark default > + read mode as AHB mode. In AHB mode, direct memory copying is > + performed. Default LUT programmed in AHB mode is Fast Read command > + with 4-byte addressing enabled. > + > config SYS_CCI400_OFFSET > hex "Offset for CCI400 base" > depends on SYS_FSL_HAS_CCI400 > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index dcd719ff0a..7c2ccfa6bc 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -242,6 +242,13 @@ config ZYNQMP_GQSPI > This option is used to enable ZynqMP QSPI controller driver which > is used to communicate with qspi flash devices. > > +config NXP_FSPI > + bool "NXP FLEXSPI driver" > + help > + Enable the NXP Flex-SPI (FSPI) driver. This driver can be used to > + access SPI NOR flash on platforms embedding this NXP IP code. > + This driver support SPI flash read, write and erase. > + > endif # if DM_SPI > > config SOFT_SPI > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 728e30c538..71f914543c 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o > obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o > obj-$(CONFIG_FSL_ESPI) += fsl_espi.o > obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o > +obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o > obj-$(CONFIG_ICH_SPI) += ich.o > obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o > obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o > diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c > new file mode 100644 > index 0000000000..9a9e6371c8 > --- /dev/null > +++ b/drivers/spi/nxp_fspi.c > @@ -0,0 +1,1088 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + * > + * NXP Flex Serial Peripheral Interface (FSPI) driver > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <spi.h> > +#include <asm/io.h> > +#include <linux/sizes.h> > +#include <dm.h> > +#include <errno.h> > +#include "nxp_fspi.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* default SCK frequency, unit: HZ */ > +#define NXP_FSPI_DEFAULT_SCK_FREQ 50000000 > + > +/* FSPI max chipselect signals number */ > +#define NXP_FSPI_MAX_CHIPSELECT_NUM 4 > + > +#define NXP_FSPI_MAX_TIMEOUT_AHBCMD 0xFF > +#define NXP_FSPI_MAX_TIMEOUT_IPCMD 0xFF > +#define NXP_FSPI_SER_CLK_DIV 0x00 > + > +#define FSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) > + > +#define FSPI_RX_MAX_IPBUF_SIZE 0x200 /* 64 * 64bits */ > +#define FSPI_TX_MAX_IPBUF_SIZE 0x400 /* 128 * 64bits */ > +#define FSPI_RX_MAX_AHBBUF_SIZE 0x800 /* 256 * 64bits */ > +#define FSPI_TX_MAX_AHBBUF_SIZE 0x40 /* 8 * 64bits */ > + > +#define TX_IPBUF_SIZE FSPI_TX_MAX_IPBUF_SIZE > +#define RX_IPBUF_SIZE FSPI_RX_MAX_IPBUF_SIZE > +#define RX_AHBBUF_SIZE FSPI_RX_MAX_AHBBUF_SIZE > +#define TX_AHBBUF_SIZE FSPI_TX_MAX_AHBBUF_SIZE > + > +/* SEQID */ > +#define SEQID_READ 0 > +#define SEQID_WREN 1 > +#define SEQID_FAST_READ 2 > +#define SEQID_RDSR 3 > +#define SEQID_SE 4 > +#define SEQID_CHIP_ERASE 5 > +#define SEQID_PP 6 > +#define SEQID_RDID 7 > +#define SEQID_BE_4K 8 > +#define SEQID_RDFSR 9 > +#define SEQID_ENTR4BYTE 10 > +#define SEQID_OCTAL_READ 11 > + > +/* FSPI CMD */ > +#define FSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ > +#define FSPI_CMD_RDSR 0x05 /* Read status register */ > +#define FSPI_CMD_RDFSR 0x70 /* Read flag status register */ > +#define FSPI_CMD_WREN 0x06 /* Write enable */ > +#define FSPI_CMD_READ 0x03 /* Read data bytes */ > +#define FSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ > +#define FSPI_CMD_OCTAL_READ 0x8b /* Octal Read (CMD-ADDR-DATA : 1-1-8) > */ > +#define FSPI_CMD_BE_4K 0x20 /* 4K erase */ > +#define FSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ > +#define FSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ > +#define FSPI_CMD_RDID 0x9f /* Read JEDEC ID */ > + > +#define FSPI_CMD_ENTR4BYTE 0xb7 /* Enter 4-Byte Address Mode */ > +#define FSPI_CMD_EXIT4BYTE 0xe9 /* Exit 4-Byte Address Mode */ > + > +/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ > +#define FSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ > +#define FSPI_CMD_OCTAL_READ_4B 0x7c /* Octal Read (CMD-ADDR-DATA : 1-1-8) > */ > +#define FSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ > +#define FSPI_CMD_BE_4K_4B 0x21 /* 4K erase */ > +#define FSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
Why all these flash command here? I think this driver can make use of spi_mem_op better try that? _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
