Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Cc: Tien Fong Chee <[email protected]>
---
 .../include/mach/reset_manager_gen5.h         |  1 +
 arch/arm/mach-socfpga/reset_manager_gen5.c    | 25 +++++++++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index dd58922cec..5e490d182e 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -9,6 +9,7 @@
 #include <dt-bindings/reset/altr,rst-mgr.h>
 
 void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
 void socfpga_bridges_reset(int enable);
 
 struct socfpga_reset_manager {
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c 
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 25baef79bc..66af924485 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -73,6 +73,28 @@ void reset_deassert_peripherals_handoff(void)
 #define L3REGS_REMAP_HPS2FPGA_MASK     0x08
 #define L3REGS_REMAP_OCRAM_MASK                0x01
 
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
+{
+       u32 brgmask = 0x0;
+       u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
+
+       if (h2f)
+               brgmask |= BIT(0);
+       else
+               l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
+
+       if (lwh2f)
+               brgmask |= BIT(1);
+       else
+               l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
+
+       if (f2h)
+               brgmask |= BIT(2);
+
+       writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
+       writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
+}
+
 void socfpga_bridges_reset(int enable)
 {
        const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
@@ -83,8 +105,7 @@ void socfpga_bridges_reset(int enable)
                /* brdmodrst */
                writel(0xffffffff, &reset_manager_base->brg_mod_reset);
        } else {
-               writel(0, &sysmgr_regs->iswgrp_handoff[0]);
-               writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+               socfpga_bridges_set_handoff_regs(false, false, false);
 
                /* Check signal from FPGA. */
                if (!fpgamgr_test_fpga_ready()) {
-- 
2.20.1

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