Hello Marek, On 4/19/19 11:47 AM, Marek Vasut wrote: > On 4/18/19 5:01 PM, Niel Fourie wrote: >> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec >> phyBOARD-Wega AM335x. >> >> CPU : AM335X-GP rev 2.1 >> Model: Phytec AM335x phyBOARD-WEGA >> DRAM: 256 MiB >> NAND: 256 MiB >> MMC: OMAP SD/MMC: 0 >> eth0: ethernet@4a100000 >> >> Working: >> - Eth0 >> - i2C >> - MMC/SD >> - NAND >> - UART >> - USB (host) >> >> Signed-off-by: Niel Fourie <[email protected]> >> --- >> arch/arm/dts/Makefile | 3 +- >> arch/arm/dts/am335x-phycore-som.dtsi | 327 ++++++++++++++++++++++ >> arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 35 +++ >> arch/arm/dts/am335x-wega-rdk.dts | 23 ++ >> arch/arm/dts/am335x-wega.dtsi | 231 +++++++++++++++ > > The DTs come from Linux kernel, but which version of Linux ? > Which exact commit ? Did you modify them in any way ? > > [...] > >> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig >> index d29f1ca0b5..9336439340 100644 >> --- a/arch/arm/mach-omap2/Kconfig >> +++ b/arch/arm/mach-omap2/Kconfig >> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig" >> source "board/ti/am335x/Kconfig" >> source "board/compulab/cm_t335/Kconfig" >> source "board/compulab/cm_t43/Kconfig" >> +source "board/phytec/phycore_pcl060/Kconfig" > > Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ? > > [1] > https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/ > [...]
This differs only by the connector. PCM variants are pluggable and PCL variants are direct soliderable to the carrier board. Copied from [1]: The PCL-060 System On Module is a connector-less, BGA style variant of the PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that support high density connectors, the PCL-060 SOM is directly soldered down to the phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). This solution offers an ultra-low cost Single Board Computer for the AM335x processor, while maintaining most of the advantages of the SOM concept. [1] https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf Thanks, Parthiban N > >> diff --git a/board/phytec/phycore_pcl060/Kconfig >> b/board/phytec/phycore_pcl060/Kconfig >> new file mode 100644 >> index 0000000000..bdd1a9b6e0 >> --- /dev/null >> +++ b/board/phytec/phycore_pcl060/Kconfig >> @@ -0,0 +1,19 @@ >> +if TARGET_PCL060 >> + >> +config SYS_BOARD >> + default "phycore_pcl060" >> + >> +config SYS_VENDOR >> + default "phytec" >> + >> +config SYS_SOC >> + default "am33xx" >> + >> +config SYS_CONFIG_NAME >> + default "phycore_pcl060" >> + >> +config PCL060_DDR_SIZE >> + int "DDR size (in MiB) of Phycore PCL060 module" >> + default 256 > > DRAM size should come from DT, we don't need another custom config > option. Look at fdtdec_setup_mem_size_base() and > fdtdec_setup_memory_banksize(). > > [...] > >> diff --git a/board/phytec/phycore_pcl060/board.c >> b/board/phytec/phycore_pcl060/board.c >> new file mode 100644 >> index 0000000000..01fe13e959 >> --- /dev/null >> +++ b/board/phytec/phycore_pcl060/board.c >> @@ -0,0 +1,340 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * board.c >> + * >> + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards >> + * >> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ >> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH >> + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH >> + * Copyright (C) 2019 DENX Software Engineering GmbH >> + */ >> + >> +#include <common.h> >> +#include <environment.h> >> +#include <errno.h> >> +#include <spl.h> >> +#include <asm/arch/cpu.h> >> +#include <asm/arch/hardware.h> >> +#include <asm/arch/omap.h> >> +#include <asm/arch/ddr_defs.h> >> +#include <asm/arch/clock.h> >> +#include <asm/arch/gpio.h> >> +#include <asm/arch/mmc_host_def.h> >> +#include <asm/arch/sys_proto.h> >> +#include <asm/io.h> >> +#include <asm/emif.h> >> +#include <asm/gpio.h> >> +#include <i2c.h> >> +#include <miiphy.h> >> +#include <cpsw.h> >> +#include <power/tps65910.h> >> +#include <jffs2/load_kernel.h> >> +#include <mtd_node.h> >> +#include <fdt_support.h> >> +#include "board.h" >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; >> + >> +#ifdef CONFIG_SPL_BUILD >> + >> +#ifdef CONFIG_SPL_OS_BOOT > > #if CONFIG_IS_ENABLED(OS_BOOT) > >> +int spl_start_uboot(void) >> +{ >> + return 1; >> +} >> +#endif >> +/* DDR RAM defines */ >> +#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */ >> + >> +#define OSC (V_OSCK / 1000000) >> +const struct dpll_params dpll_ddr = { >> + DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1}; >> + >> +const struct dpll_params *get_dpll_ddr_params(void) >> +{ >> + return &dpll_ddr; >> +} >> + >> +const struct ctrl_ioregs ioregs = { >> + .cm0ioctl = 0x18B, >> + .cm1ioctl = 0x18B, >> + .cm2ioctl = 0x18B, >> + .dt0ioctl = 0x18B, >> + .dt1ioctl = 0x18B, >> +}; >> + >> +static const struct cmd_control ddr3_cmd_ctrl_data = { >> + .cmd0csratio = 0x80, >> + .cmd0iclkout = 0x0, >> + >> + .cmd1csratio = 0x80, >> + .cmd1iclkout = 0x0, >> + >> + .cmd2csratio = 0x80, >> + .cmd2iclkout = 0x0, >> +}; >> + >> +#if CONFIG_PCL060_DDR_SIZE == 256 > > Get the DRAM layout from DT and apply EMIF settings accordingly. > > [...] > >> diff --git a/include/configs/phycore_pcl060.h >> b/include/configs/phycore_pcl060.h >> new file mode 100644 >> index 0000000000..982c96b267 >> --- /dev/null >> +++ b/include/configs/phycore_pcl060.h >> @@ -0,0 +1,141 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * phycore_pcl060.h >> + * >> + * Phytec phyCORE-AM335x (pcl060) boards information header >> + * >> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ >> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH >> + * Copyright (C) 2019 DENX Software Engineering GmbH >> + */ >> + >> +#ifndef __CONFIG_PCL060_H >> +#define __CONFIG_PCL060_H >> + >> +#include <configs/ti_am335x_common.h> >> + >> +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ >> +#define CONFIG_MACH_TYPE MACH_TYPE_PCL060 >> +#define CONFIG_SYS_MMC_ENV_DEV 0 >> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 >> + >> +#ifdef CONFIG_NAND >> +#define NANDARGS \ >> + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ >> + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ >> + "nandargs=setenv bootargs console=${console} " \ >> + "${optargs} " \ >> + "root=${nandroot} " \ >> + "rootfstype=${nandrootfstype}\0" \ >> + "nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \ >> + "nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \ >> + "nandboot=echo Booting from nand ...; " \ >> + "run nandargs; " \ >> + "ubi part NAND.UBI; " \ >> + "ubi readvol ${fdtaddr} oftree; " \ >> + "ubi readvol ${loadaddr} kernel; " \ >> + "bootz ${loadaddr} - ${fdtaddr}\0" >> + >> +#else >> +#define NANDARGS "" >> +#endif >> + >> +/* set to negative value for no autoboot */ >> +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ >> + "bootcmd_" #devtypel #instance "=" \ >> + "setenv mmcdev " #instance "; "\ >> + "setenv bootpart " #instance ":1 ; "\ >> + "setenv rootpart " #instance ":2 ; "\ >> + "run mmcboot\0" >> + >> +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ >> + #devtypel #instance " " >> + >> +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ >> + "bootcmd_" #devtypel #instance "=" \ >> + "run nandboot\0" >> + >> +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ >> + #devtypel #instance " " >> + >> +#define BOOT_TARGET_DEVICES(func) \ >> + func(MMC, mmc, 0) \ >> + func(LEGACY_MMC, legacy_mmc, 0) \ >> + func(MMC, mmc, 1) \ >> + func(LEGACY_MMC, legacy_mmc, 1) \ >> + func(NAND, nand, 0) >> + >> +#include <config_distro_bootcmd.h> >> +#include <environment/ti/dfu.h> >> +#include <environment/ti/mmc.h> >> + >> +#define CONFIG_EXTRA_ENV_SETTINGS \ >> + DEFAULT_MMC_TI_ARGS \ >> + DEFAULT_LINUX_BOOT_ENV \ >> + "bootfile=zImage\0" \ >> + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ >> + "console=ttyO0,115200n8\0" \ >> + "optargs=\0" \ >> + "mmcrootfstype=ext2 rootwait\0" \ >> + "finduuid=part uuid mmc ${rootpart} uuid\0" \ >> + "boot_fit=0\0" \ >> + NANDARGS \ >> + BOOTENV >> + >> +/* Clock Defines */ >> +#define V_OSCK 25000000 /* Clock output from >> T2 */ >> +#define V_SCLK (V_OSCK) >> + >> +#define CONFIG_POWER_TPS65910 >> + >> +#ifdef CONFIG_NAND >> +/* NAND: device related configs */ >> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE >> +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ >> + CONFIG_SYS_NAND_PAGE_SIZE) >> +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 >> +#define CONFIG_SYS_NAND_OOBSIZE 64 >> +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) >> +/* NAND: driver related configs */ >> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS >> +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ >> + 10, 11, 12, 13, 14, 15, 16, 17, \ >> + 18, 19, 20, 21, 22, 23, 24, 25, \ >> + 26, 27, 28, 29, 30, 31, 32, 33, \ >> + 34, 35, 36, 37, 38, 39, 40, 41, \ >> + 42, 43, 44, 45, 46, 47, 48, 49, \ >> + 50, 51, 52, 53, 54, 55, 56, 57, } >> + >> +#define CONFIG_SYS_NAND_ECCSIZE 512 >> +#define CONFIG_SYS_NAND_ECCBYTES 14 >> +#define CONFIG_SYS_NAND_ONFI_DETECTION >> +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW >> + >> +/* NAND: SPL related configs */ >> +#ifdef CONFIG_SPL_OS_BOOT >> +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ >> +#endif >> +#endif /* !CONFIG_NAND */ >> + >> +#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ >> +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } > > I think there's a default value for that in include/config_fallbacks.h , > why do you override it here ? > >> +/* CPU */ >> + >> +#ifdef CONFIG_SPI_BOOT >> +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 >> +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 >> +#elif defined(CONFIG_ENV_IS_IN_NAND) >> +#define CONFIG_ENV_OFFSET 0x000a0000 >> +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE >> +#endif >> + >> +/* >> + * USB configuration >> + */ >> +#define CONFIG_AM335X_USB0 >> +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL >> +#define CONFIG_AM335X_USB1 >> +#define CONFIG_AM335X_USB1_MODE MUSB_HOST > > Can't the USB settings be extracted from DT ? > -- Thanks, Parthiban N DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: [email protected] _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
