Hi Christophe, > > Called to configure Ethernet PHY interface selection and configure clock > selection > in RCC Ethernet clock tree. > > Signed-off-by: Christophe Roullier <[email protected]> > --- > > board/st/stm32mp1/stm32mp1.c | 77 > ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c > index 54feca0..7c37018 100644 > --- a/board/st/stm32mp1/stm32mp1.c > +++ b/board/st/stm32mp1/stm32mp1.c > @@ -10,12 +10,27 @@ > #include <generic-phy.h> > #include <phy.h> > #include <reset.h> > +#include <syscon.h> > #include <usb.h> > #include <asm/arch/stm32.h> > #include <asm/io.h> > #include <power/regulator.h> > #include <usb/dwc2_udc.h> > > +/* SYSCFG registers */ > +#define SYSCFG_PMCSETR 0x04 > +#define SYSCFG_PMCCLRR 0x44 > + > +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) > +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) > + > +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) > + > +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) > +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 > +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) > +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) > + > /* > * Get a global data pointer > */ > @@ -196,3 +211,65 @@ int board_init(void) > > return 0; > } > + > +/* board interface eth init */ > +/* this is a weak define that we are overriding */ int > +board_interface_eth_init(int interface_type, bool eth_clk_sel_reg, > + bool eth_ref_clk_sel_reg) > +{ > + u8 *syscfg; > + u32 value; > + > + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); > + > + if (!syscfg) > + return -ENODEV; > + > + switch (interface_type) { > + case PHY_INTERFACE_MODE_MII: > + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | > + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; > + debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); > + break; > + case PHY_INTERFACE_MODE_GMII: > + if (eth_clk_sel_reg) > + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | > + SYSCFG_PMCSETR_ETH_CLK_SEL; > + else > + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; > + debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); > + break; > + case PHY_INTERFACE_MODE_RMII: > + if (eth_ref_clk_sel_reg) > + value = SYSCFG_PMCSETR_ETH_SEL_RMII | > + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; > + else > + value = SYSCFG_PMCSETR_ETH_SEL_RMII; > + debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); > + break; > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + if (eth_clk_sel_reg) > + value = SYSCFG_PMCSETR_ETH_SEL_RGMII | > + SYSCFG_PMCSETR_ETH_CLK_SEL; > + else > + value = SYSCFG_PMCSETR_ETH_SEL_RGMII; > + debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); > + break; > + default: > + debug("%s: Do not manage %d interface\n", > + __func__, interface_type); > + /* Do not manage others interfaces */ > + return -EINVAL; > + } > + > + /* clear and set ETH configuration bits */ > + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | > SYSCFG_PMCSETR_ETH_SELMII | > + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | > SYSCFG_PMCSETR_ETH_CLK_SEL, > + syscfg + SYSCFG_PMCCLRR); > + writel(value, syscfg + SYSCFG_PMCSETR); > + > + return 0; > +} > -- > 2.7.4
For stm32mp1 boards EV1 and DK2 Test done with master (SHA1 = 75ce8c938d39bd22460be66e6bf318bd2410c17b) Tested-by: Patrick Delaunay <[email protected]> Acked-by: Patrick Delaunay <[email protected]> Regards Patrick _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
