> The logic in the main transmit loop took a bit of reading the TRM to > fully understand (due to silent assumptions based in internal logic): > the "wait until idle" at the end of each iteration through the loop is > required for the transmit-path as each clearing of the ENA register > (to update run-length in the CTRLR1 register) will implicitly flush > the FIFOs... transmisson can therefore not overlap loop iterations. > > This change adds a comment to clarify the reason/need for waiting > until the controller becomes idle and wraps the entire check into an > 'if (out)' to make it clear that this is required for transfers with a > transmit-component only (for transfers having a receive-component, > completion of the transmit-side is trivially ensured by having > received the correct number of bytes). > > The change does not increase execution time measurably in any of my > tests. > > Signed-off-by: Philipp Tomsich <[email protected]> > --- > > drivers/spi/rk_spi.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) >
Applied to u-boot-rockchip, thanks! _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
