> -----Original Message----- > From: Meenakshi Aggarwal <[email protected]> > Sent: Tuesday, May 28, 2019 9:38 PM > To: [email protected]; Prabhakar Kushwaha > <[email protected]> > Cc: Meenakshi Aggarwal <[email protected]>; Udit Kumar > <[email protected]> > Subject: [PATCH v3] armv8/fsl-layerscape: Add loop to check L3 dcache status > > Flushing L3 cache may need variable time depending upon cache line allocation. > > Coming up with a proper timeout value would be best handled by simulations > under multiple scenarios in your actual system. > From the purely HN-F point of view, the flush would take ~15 cycles for a > clean > line, and ~22 cycles for a dirty line. For the dirty line case, there are > many > variables outside the HN-F that will increase the duration per line. For > example, > a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX > RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst- > case timeout would have to factor in all of these variables plus the HN-F > cycles > for every line in the L3, and assuming all lines are dirty > > In case if L3 is not flushed properly, system behaviour will be erratic, so > remove > timeout and add loop to check status of L3 cache. > > System will stuck in while loop if there is some issue in L3 cache flushing. > > Signed-off-by: Udit Kumar <[email protected]> > Signed-off-by: Meenakshi Aggarwal <[email protected]> > > --- > changed for v2: > - An increase in timeout doesn't ensure completion of > L3 cache flushing operation. So checking the L3 cache > status till it succedd. > > changed for v3: > - Updated Copyright > - add loop to poll for l3 dcache status in hnf_pstate_poll > function > - removed timeout related code as it is not needed > ---
This patch has been applied to fsl-qoriq master, awaiting upstream. --pk _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
