The veyron_init() should go to its board file veyron.c, and the board_early_init_f() could be the right place.
Signed-off-by: Kever Yang <[email protected]> --- arch/arm/mach-rockchip/rk3288-board.c | 65 --------------------------- board/google/veyron/veyron.c | 63 ++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 65 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index e629df3abb..915f82e8ba 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -15,7 +15,6 @@ #include <asm/arch-rockchip/pmu_rk3288.h> #include <asm/arch-rockchip/boot_mode.h> #include <asm/gpio.h> -#include <dt-bindings/clock/rk3288-cru.h> #include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; @@ -70,73 +69,9 @@ int board_late_init(void) return rk_board_late_init(); } -#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) -static int veyron_init(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } - - /* Slowly raise to max CPU voltage to prevent overshoot */ - ret = regulator_set_value(dev, 1200000); - if (ret) - return ret; - udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ - ret = regulator_set_value(dev, 1400000); - if (ret) - return ret; - udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ - - ret = rockchip_get_clk(&clk.dev); - if (ret) - return ret; - clk.id = PLL_APLL; - ret = clk_set_rate(&clk, 1800000000); - if (IS_ERR_VALUE(ret)) - return ret; - - ret = regulator_get_by_platname("vcc33_sd", &dev); - if (ret) { - debug("Cannot get regulator name\n"); - return ret; - } - - ret = regulator_set_value(dev, 3300000); - if (ret) - return ret; - - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } - - return 0; -} -#endif - int board_init(void) { -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) return 0; -#else - int ret; - - /* We do some SoC one time setting here */ - if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { - ret = veyron_init(); - if (ret) - return ret; - } - - return 0; -#endif } #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 361f0e9da2..dd2c014c60 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -3,20 +3,82 @@ * (C) Copyright 2015 Google, Inc */ +#include <clk.h> #include <common.h> +#include <dm.h> #include <asm/arch-rockchip/clock.h> +#include <dt-bindings/clock/rk3288-cru.h> +#include <power/regulator.h> /* * We should increase the DDR voltage to 1.2V using the PWM regulator. * There is a U-Boot driver for this but it may need to add support for the * 'voltage-table' property. */ +#ifndef CONFIG_SPL_BUILD +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) +static int veyron_init(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = regulator_get_by_platname("vdd_arm", &dev); + if (ret) { + debug("Cannot set regulator name\n"); + return ret; + } + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = regulator_set_value(dev, 1200000); + if (ret) + return ret; + udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ + ret = regulator_set_value(dev, 1400000); + if (ret) + return ret; + udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ + + ret = rockchip_get_clk(&clk.dev); + if (ret) + return ret; + clk.id = PLL_APLL; + ret = clk_set_rate(&clk, 1800000000); + if (IS_ERR_VALUE(ret)) + return ret; + + ret = regulator_get_by_platname("vcc33_sd", &dev); + if (ret) { + debug("Cannot get regulator name\n"); + return ret; + } + + ret = regulator_set_value(dev, 3300000); + if (ret) + return ret; + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulators\n", __func__); + return ret; + } + + return 0; +} +#endif int board_early_init_f(void) { struct udevice *dev; int ret; +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { + ret = veyron_init(); + if (ret) + return ret; + } +#endif /* * This init is done in SPL, but when chain-loading U-Boot SPL will * have been skipped. Allow the clock driver to check if it needs @@ -30,3 +92,4 @@ int board_early_init_f(void) return 0; } +#endif -- 2.17.1 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
