On Mon, 2019-08-05 at 09:33 +0300, Ramon Fried wrote:
> On Sun, Aug 4, 2019 at 8:25 PM Frank Wunderlich <fran...@public-files.de>
> wrote:
> >
> > From: Ryder Lee <ryder....@mediatek.com>
> >
> > This adds PCIe controller support for MT7623.
> >
> > Tested-by: Frank Wunderlich <fran...@public-files.de>
> > Signed-off-by: Frank Wunderlich <fran...@public-files.de>
> > Signed-off-by: Ryder Lee <ryder....@mediatek.com>
> > ---
> > drivers/pci/Kconfig | 8 +
> > drivers/pci/Makefile | 1 +
> > drivers/pci/pcie_mediatek.c | 292 ++++++++++++++++++++++++++++++++++++
> > 3 files changed, 301 insertions(+)
> > create mode 100644 drivers/pci/pcie_mediatek.c
> >
> > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> > index 3fe38f7315..6f19471ae7 100644
> > --- a/drivers/pci/Kconfig
> > +++ b/drivers/pci/Kconfig
> > @@ -145,4 +145,12 @@ config PCI_MVEBU
> > Say Y here if you want to enable PCIe controller support on
> > Armada XP/38x SoCs.
> >
> > +config PCIE_MEDIATEK
> > + bool "MediaTek PCIe controller"
> > + depends on DM_PCI
> > + depends on ARCH_MEDIATEK
> > + help
> > + Say Y here if you want to enable PCIe controller support on
> > + MediaTek SoCs.
> This is too generic, is there a version number ? who is the IP vendor
> behind that Mediatek PCIe ? on which mediatek SoCs ?
No meaningful version number, and here is a copy-paste from Linux
version and we use single driver for different generation IPs (via soc
data):
static const struct of_device_id mtk_pcie_ids[] = {
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
{},
};
We can modify the description if you think this is better- something
like this:
Say Y here if you want to enable gen2 v1 PCIe controller, which could be
found on MT7623 SoC family.
> > +
> > endif
> > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> > index b5ebd50c85..7093d63918 100644
> > --- a/drivers/pci/Makefile
> > +++ b/drivers/pci/Makefile
> > @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) +=
> > pcie_layerscape_gen4.o \
> > pcie_layerscape_gen4_fixup.o
> > obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
> > obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
> > +obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
> > diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c
> > new file mode 100644
> > index 0000000000..3f24060d26
> > --- /dev/null
> > +++ b/drivers/pci/pcie_mediatek.c
> > @@ -0,0 +1,292 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * MediaTek PCIe host controller driver.
> > + *
> > + * Copyright (c) 2017-2019 MediaTek Inc.
> > + * Author: Ryder Lee <ryder....@mediatek.com>
> > + * Honghui Zhang <honghui.zh...@mediatek.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <clk.h>
> > +#include <dm.h>
> > +#include <generic-phy.h>
> > +#include <pci.h>
> > +#include <reset.h>
> > +#include <asm/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/list.h>
> > +
> > +/* PCIe shared registers */
> > +#define PCIE_SYS_CFG 0x00
> > +#define PCIE_INT_ENABLE 0x0c
> > +#define PCIE_CFG_ADDR 0x20
> > +#define PCIE_CFG_DATA 0x24
> > +
> > +/* PCIe per port registers */
> > +#define PCIE_BAR0_SETUP 0x10
> > +#define PCIE_CLASS 0x34
> > +#define PCIE_LINK_STATUS 0x50
> > +
> > +#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
> > +#define PCIE_PORT_PERST(x) BIT(1 + (x))
> > +#define PCIE_PORT_LINKUP BIT(0)
> > +#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
> > +
> > +#define PCIE_BAR_ENABLE BIT(0)
> > +#define PCIE_REVISION_ID BIT(0)
> > +#define PCIE_CLASS_CODE (0x60400 << 8)
> > +#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
> > + ((((regn) >> 8) & GENMASK(3, 0)) << 24))
> > +#define PCIE_CONF_ADDR(regn, bdf) \
> > + (PCIE_CONF_REG(regn) | (bdf))
> > +
> > +/* MediaTek specific configuration registers */
> > +#define PCIE_FTS_NUM 0x70c
> > +#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
> > +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
> > +
> > +#define PCIE_FC_CREDIT 0x73c
> > +#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
> > +#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
> > +
> > +struct mtk_pcie_port {
> > + void __iomem *base;
> > + struct list_head list;
> > + struct mtk_pcie *pcie;
> > + struct reset_ctl reset;
> > + struct clk sys_ck;
> > + struct phy phy;
> > + u32 slot;
> > +};
> > +
> > +struct mtk_pcie {
> > + void __iomem *base;
> > + struct clk free_ck;
> > + struct list_head ports;
> > +};
> > +
> > +static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf,
> > + uint offset, void **paddress)
> > +{
> > + struct mtk_pcie *pcie = dev_get_priv(udev);
> > +
> > + writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
> > + *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
> > + uint offset, ulong *valuep,
> > + enum pci_size_t size)
> > +{
> > + return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
> > + bdf, offset, valuep, size);
> > +}
> > +
> > +static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
> > + uint offset, ulong value,
> > + enum pci_size_t size)
> > +{
> > + return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
> > + bdf, offset, value, size);
> > +}
> > +
> > +static const struct dm_pci_ops mtk_pcie_ops = {
> > + .read_config = mtk_pcie_read_config,
> > + .write_config = mtk_pcie_write_config,
> > +};
> > +
> > +static void mtk_pcie_port_free(struct mtk_pcie_port *port)
> > +{
> > + list_del(&port->list);
> > + free(port);
> > +}
> > +
> > +static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
> > +{
> > + struct mtk_pcie *pcie = port->pcie;
> > + u32 slot = PCI_DEV(port->slot << 11);
> > + u32 val;
> > + int err;
> > +
> > + /* assert port PERST_N */
> > + val = readl(pcie->base + PCIE_SYS_CFG);
> > + val |= PCIE_PORT_PERST(port->slot);
> > + writel(val, pcie->base + PCIE_SYS_CFG);
> > +
> > + /* de-assert port PERST_N */
> > + val = readl(pcie->base + PCIE_SYS_CFG);
> > + val &= ~PCIE_PORT_PERST(port->slot);
> > + writel(val, pcie->base + PCIE_SYS_CFG);
> > +
> > + /* 100ms timeout value should be enough for Gen1/2 training */
> > + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
> > + !!(val & PCIE_PORT_LINKUP), 100000);
> > + if (err)
> > + return -ETIMEDOUT;
> > +
> > + /* disable interrupt */
> > + val = readl(pcie->base + PCIE_INT_ENABLE);
> > + val &= ~PCIE_PORT_INT_EN(port->slot);
> > + writel(val, pcie->base + PCIE_INT_ENABLE);
> You might want to consider using setbits_le32/clrbits_le32.
@Frank, could you please switch all the w/r into set/clrbits_le32 ?
Ryder
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