Add the glue code to allow the rk3308 variant of the Rockchip gmac
to provide network functionality.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 65 +++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index d2c52b4c46..e152faf083 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -17,6 +17,7 @@
#include <asm/arch-rockchip/grf_px30.h>
#include <asm/arch-rockchip/grf_rk322x.h>
#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rk3308/grf_rk3308.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/arch-rockchip/grf_rk3368.h>
#include <asm/arch-rockchip/grf_rk3399.h>
@@ -173,6 +174,47 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
+static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3308_grf *grf;
+ struct clk clk_speed;
+ int speed, ret;
+ enum {
+ RK3308_GMAC_SPEED_SHIFT = 0x0,
+ RK3308_GMAC_SPEED_MASK = BIT(0),
+ RK3308_GMAC_SPEED_10M = 0,
+ RK3308_GMAC_SPEED_100M = BIT(0),
+ };
+
+ ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
+ &clk_speed);
+ if (ret)
+ return ret;
+
+ switch (priv->phydev->speed) {
+ case 10:
+ speed = RK3308_GMAC_SPEED_10M;
+ ret = clk_set_rate(&clk_speed, 2500000);
+ if (ret)
+ return ret;
+ break;
+ case 100:
+ speed = RK3308_GMAC_SPEED_100M;
+ ret = clk_set_rate(&clk_speed, 25000000);
+ if (ret)
+ return ret;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed);
+
+ return 0;
+}
+
static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3328_grf_regs *grf;
@@ -377,6 +419,22 @@ static void rk3288_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3308_grf *grf;
+ enum {
+ RK3308_GMAC_PHY_INTF_SEL_SHIFT = 2,
+ RK3308_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 2),
+ RK3308_GMAC_PHY_INTF_SEL_RMII = BIT(4),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ rk_clrsetreg(&grf->mac_con0,
+ RK3308_GMAC_PHY_INTF_SEL_MASK,
+ RK3308_GMAC_PHY_INTF_SEL_RMII);
+}
+
static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3328_grf_regs *grf;
@@ -646,6 +704,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops rk3308_gmac_ops = {
+ .fix_mac_speed = rk3308_gmac_fix_mac_speed,
+ .set_to_rmii = rk3308_gmac_set_to_rmii,
+};
+
const struct rk_gmac_ops rk3328_gmac_ops = {
.fix_mac_speed = rk3328_gmac_fix_mac_speed,
.set_to_rgmii = rk3328_gmac_set_to_rgmii,
@@ -673,6 +736,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
.data = (ulong)&rk3228_gmac_ops },
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)&rk3288_gmac_ops },
+ { .compatible = "rockchip,rk3308-mac",
+ .data = (ulong)&rk3308_gmac_ops },
{ .compatible = "rockchip,rk3328-gmac",
.data = (ulong)&rk3328_gmac_ops },
{ .compatible = "rockchip,rk3368-gmac",
--
2.19.1
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