On Wed, Jan 22, 2020 at 4:03 AM Marek Vasut <ma...@denx.de> wrote:
>
> From: Masahiro Yamada <yamada.masah...@socionext.com>
>
> The "nand_x" and "ecc" clocks are currently optional. Make the core
> clock optional in the same way. This will allow platforms with no clock
> driver support to use this driver.
>
> Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
> Tested-by: Marek Vasut <ma...@denx.de> # On SoCFPGA Arria V
Applied to u-boot-uniphier.
Thanks.
> ---
> V2: No change
> ---
> drivers/mtd/nand/raw/denali_dt.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/denali_dt.c
> b/drivers/mtd/nand/raw/denali_dt.c
> index 0ce81324b9..b1e14982c4 100644
> --- a/drivers/mtd/nand/raw/denali_dt.c
> +++ b/drivers/mtd/nand/raw/denali_dt.c
> @@ -91,7 +91,7 @@ static int denali_dt_probe(struct udevice *dev)
> if (ret)
> ret = clk_get_by_index(dev, 0, &clk);
> if (ret)
> - return ret;
> + clk.dev = NULL;
>
> ret = clk_get_by_name(dev, "nand_x", &clk_x);
> if (ret)
> @@ -101,9 +101,11 @@ static int denali_dt_probe(struct udevice *dev)
> if (ret)
> clk_ecc.dev = NULL;
>
> - ret = clk_enable(&clk);
> - if (ret)
> - return ret;
> + if (clk.dev) {
> + ret = clk_enable(&clk);
> + if (ret)
> + return ret;
> + }
>
> if (clk_x.dev) {
> ret = clk_enable(&clk_x);
> --
> 2.24.1
>
--
Best Regards
Masahiro Yamada
