On Tue, Feb 11, 2020 at 2:05 PM Sean Anderson <[email protected]> wrote: > > Some older processors (notably the Kendryte K210) use an older version of > the RISC-V privileged specification. The primary changes between the old > and new are in virtual memory, and in the merging of three separate counter > enable CSRs. Using the new CSR on an old processor causes an illegal > instruction exception. This patch adds an option to use the old CSRs > instead of the new one. > > Signed-off-by: Sean Anderson <[email protected]> > --- > > Changes in v4: > - Fixed CSRs not being defined properly (thanks bmeng) > - Added ifdefs for all changed CSRs (e.g. for VM) > - Also properly disable VM on boot > > Changes in v3: > - Renamed from "riscv: Add option to disable writes to mcounteren" > - Added original functionality back for older priv specs. > > Changes in v2: > - Moved forward in the patch series > > arch/riscv/Kconfig | 10 +++++++++ > arch/riscv/cpu/cpu.c | 9 ++++++++ > arch/riscv/include/asm/csr.h | 40 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 59 insertions(+) >
Reviewed-by: Bin Meng <[email protected]>
