On 12. 03. 20 9:22, Marek Vasut wrote: > On 3/12/20 9:20 AM, Michal Simek wrote: >> On 12. 03. 20 9:17, Marek Vasut wrote: >>> On 3/12/20 9:14 AM, Michal Simek wrote: >>>> rev1.1 has different DDR sodimm module that's why it requires different DDR >>>> configuration. >>> >>> Can't you move the DRAM configuration to DT at some point ? >>> >> >> That algorithm is not available. In this zcu102 case the part of code is >> available in fsbl (which is not gpl) but it just changing some >> parameters between sodimm on rev1 and rev1.1. It doesn't contain full >> algorithm how to configure the whole ddr controller. > > Surely Xilinx knows the algorithm , since they developed the chip and > the controller ? :)
You know the answer that's why no reason to answer it. And I am not aware about any activity to move DDR generation to any first stage bootloader and the standard way available is to configure DDR controller via psu_init* files. Thanks, Michal
