Re: [PATCH v1 02/10] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM

[Stefan Roese]

On 13.05.20 14:59, Daniel Schwierzeck wrote:

Am 02.05.20 um 10:59 schrieb Stefan Roese:

This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese <s...@denx.de>
---

  arch/mips/lib/cache.c | 13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1a8c87d094..9e20b39608 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,7 +7,7 @@
  #include <common.h>
  #include <cpu_func.h>
  #include <asm/cacheops.h>
-#ifdef CONFIG_MIPS_L2_CACHE
+#ifdef CONFIG_MIPS_CM
  #include <asm/cm.h>
  #endif
  #include <asm/io.h>
@@ -16,6 +16,17 @@

DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_MIPS_L2_CACHE) && !defined(CONFIG_MIPS_CM)

+/*
+ * Dummy implementation to avoid compile warning on platforms with L2
+ * cache but without CM
+ */
+static unsigned long mips_cm_l2_line_size(void)
+{
+       return 0;
+}
+#endif
+
  static void probe_l2(void)
  {
  #ifdef CONFIG_MIPS_L2_CACHE

to avoid further cluttering with #ifdefs I would rather change cm.h like
so and drop the guard around #include <asm/cm.h>:

#if CONFIG_IS_ENABLED(MIPS_CM)
static inline void *mips_cm_base(void)
{
        return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
}

static inline unsigned long mips_cm_l2_line_size(void)
{
        unsigned long l2conf, line_sz;

        l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG);

        line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT;
        line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
        return line_sz ? (2 << line_sz) : 0;
}
#else
static inline void *mips_cm_base(void)
{
        return NULL;
}

static inline unsigned long mips_cm_l2_line_size(void)
{
        return 0;
}
#endif

Okay, will do in v2.

Thanks,
Stefan