Some settings were modified slightly in the device-tree conversion. Return these to their original values.
Signed-off-by: Simon Glass <[email protected]> --- arch/x86/dts/chromebook_coral.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index aad12f2c4d..5ee056fc95 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -517,6 +517,11 @@ 20 23 22 21 18 19 16 17 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 25 28 30 31 26 27 24 29>; + + fspm,dimm0-spd-address = <0>; + fspm,dimm1-spd-address = <0>; + fspm,skip-cse-rbp = <1>; + fspm,enable-s3-heci2 = <0>; }; &fsp_s { -- 2.27.0.rc0.183.gde8f92d652-goog
