Some settings were modified slightly in the device-tree conversion. Return
these to their original values.

Signed-off-by: Simon Glass <s...@chromium.org>
---

Changes in v2: None

 arch/x86/dts/chromebook_coral.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/dts/chromebook_coral.dts 
b/arch/x86/dts/chromebook_coral.dts
index dea35b73a0..fe0d4dedd7 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -516,6 +516,11 @@
                20 23 22 21 18 19 16 17
                /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
                25 28 30 31 26 27 24 29>;
+
+       fspm,dimm0-spd-address = <0>;
+       fspm,dimm1-spd-address = <0>;
+       fspm,skip-cse-rbp = <1>;
+       fspm,enable-s3-heci2 = <0>;
 };
 
 &fsp_s {
-- 
2.27.0.rc0.183.gde8f92d652-goog

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