Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam <sagar.ka...@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.pa...@sifive.com> Reviewed-by: Bin Meng <bin.m...@windriver.com> --- include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3 +/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif -- 2.7.4
