On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.ka...@sifive.com> wrote: > > Hi Jagan, > > > -----Original Message----- > > From: Jagan Teki <ja...@amarulasolutions.com> > > Sent: Thursday, June 25, 2020 11:13 PM > > To: Sagar Kadam <sagar.ka...@sifive.com> > > Cc: U-Boot-Denx <u-boot@lists.denx.de>; Rick Chen <r...@andestech.com>; > > Paul Walmsley ( Sifive) <paul.walms...@sifive.com>; Palmer Dabbelt > > <pal...@dabbelt.com>; Anup Patel <anup.pa...@wdc.com>; Atish Patra > > <atish.pa...@wdc.com>; Lukasz Majewski <lu...@denx.de>; Pragnesh > > Patel <pragnesh.pa...@sifive.com>; bin.m...@windriver.com; Simon Glass > > <s...@chromium.org>; Trevor Woerner <twoer...@gmail.com>; Eugeniy > > Paltsev <eugeniy.palt...@synopsys.com>; Patrick Wildt > > <patr...@blueri.se>; Weijie Gao <weijie....@mediatek.com>; Fabio > > Estevam <feste...@gmail.com> > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals > > available in prci > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > > <sagar.ka...@sifive.com> wrote: > > > > > > Add bit indexes for reset signals within the PRCI module > > > on FU540-C000 SoC. > > > The DDR and ethernet sub-system's have reset signals > > > indicated by these reset indexes. > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.ka...@sifive.com> > > > Reviewed-by: Pragnesh Patel <pragnesh.pa...@sifive.com> > > > Reviewed-by: Bin Meng <bin.m...@windriver.com> > > > --- > > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt- > > bindings/clock/sifive-fu540-prci.h > > > index 6a0b70a..1c03b09 100644 > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > > @@ -15,4 +15,12 @@ > > > #define PRCI_CLK_GEMGXLPLL 2 > > > #define PRCI_CLK_TLCLK 3 > > > > > > +/* Reset bit indexes to be used by driver */ > > > +#define PRCI_RST_DDR_CTRL_N 0 > > > +#define PRCI_RST_DDR_AXI_N 1 > > > +#define PRCI_RST_DDR_AHB_N 2 > > > +#define PRCI_RST_DDR_PHY_N 3 > > > +/* bit 4 is reserved bit */ > > > +#define PRCI_RST_RSVD_N 4 > > > +#define PRCI_RST_GEMGXL_N 5 > > > #endif > > > > Do these bindings are synced from Linux? If Yes better to sync with a > > particular commit or tag rather than patch. > > > > No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux. Jagan.
