[PATCH 08/17] x86: Do cache set-up by default when booting from coreboot

[Simon Glass]

A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.

If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.

Signed-off-by: Simon Glass <s...@chromium.org>
---

 arch/x86/lib/init_helpers.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 67401b9ba79..0c55544a670 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -18,10 +18,7 @@ int init_cache_f_r(void)
                 IS_ENABLED(CONFIG_FSP_VERSION2);
        int ret;
 
-       if (!ll_boot_init())
-               return 0;
-
-       do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
+       do_mtrr &= !IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_FSP_VERSION1) 
&&
                !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
 
        if (do_mtrr) {
-- 
2.31.0.208.g409f899ff0-goog