On 5/25/21 8:30 AM, Andre Przywara wrote: > When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about > pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which > are always below 1GB on all Allwinner SoCs, so there is no problem with > anything having more than 32 bits. > > Add the proper casts to make it compile cleanly. > > Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Jaehoon Chung <jh80.ch...@samsung.com> Best Regards, Jaehoon Chung > --- > drivers/mmc/sunxi_mmc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c > index 87b79fcf5ef..869af993d35 100644 > --- a/drivers/mmc/sunxi_mmc.c > +++ b/drivers/mmc/sunxi_mmc.c > @@ -631,14 +631,14 @@ static int sunxi_mmc_probe(struct udevice *dev) > cfg->f_min = 400000; > cfg->f_max = 52000000; > > - priv->reg = (void *)dev_read_addr(dev); > + priv->reg = dev_read_addr_ptr(dev); > > /* We don't have a sunxi clock driver so find the clock address here */ > ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, > 1, &args); > if (ret) > return ret; > - ccu_reg = (u32 *)ofnode_get_addr(args.node); > + ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node); > > priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; > priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4; >
