On Mai 27 2021, Green Wan wrote:
> +/* List of clock controls provided by the PRCI */
> +struct __prci_clock __prci_init_clocks_fu740[] = {
> + [PRCI_CLK_COREPLL] = {
> + .name = "corepll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_corepll_data,
> + },
> + [PRCI_CLK_DDRPLL] = {
> + .name = "ddrpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_ddrpll_data,
> + },
> + [PRCI_CLK_GEMGXLPLL] = {
> + .name = "gemgxlpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_gemgxlpll_data,
> + },
> + [PRCI_CLK_DVFSCOREPLL] = {
> + .name = "dvfscorepll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_dvfscorepll_data,
> + },
> + [PRCI_CLK_HFPCLKPLL] = {
> + .name = "hfpclkpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_hfpclkpll_data,
> + },
> + [PRCI_CLK_CLTXPLL] = {
> + .name = "cltxpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_cltxpll_data,
> + },
> + [PRCI_CLK_TLCLK] = {
> + .name = "tlclk",
> + .parent_name = "corepll",
> + .ops = &sifive_fu740_prci_tlclksel_clk_ops,
> + },
> + [PRCI_CLK_PCLK] = {
> + .name = "pclk",
> + .parent_name = "hfpclkpll",
> + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
> + },
> + [PRCI_CLK_PCIEAUX] {
> + .name = "pciaux",
Shouldn't that be called "pcieaux"?
Andreas.
--
Andreas Schwab, [email protected]
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