On Tue, Sep 14, 2021 at 08:28:24PM +0200, Marek Vasut wrote:
> Before e2e95e5e254 ("spi: Update speed/mode on change") most systems
> silently defaulted to SF bus mode 0. Now the mode is always updated,
> which causes breakage. It seems most SF which are used as boot media
> operate in bus mode 0, so switch that as the default.
>
> This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx
> ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble
> with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked
> as those might need mode 3.
>
> Signed-off-by: Marek Vasut <[email protected]>
> Cc: Aleksandar Gerasimovski <[email protected]>
> Cc: Andreas Biessmann <[email protected]>
> Cc: Eugen Hristev <[email protected]>
> Cc: Michal Simek <[email protected]>
> Cc: Patrice Chotard <[email protected]>
> Cc: Patrick Delaunay <[email protected]>
> Cc: Peng Fan <[email protected]>
> Cc: Siew Chin Lim <[email protected]>
> Cc: Tom Rini <[email protected]>
> Cc: Valentin Longchamp <[email protected]>
> Cc: Vignesh Raghavendra <[email protected]>Applied to u-boot/master, thanks! -- Tom
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