On 24.09.21 22:59, Marek Behún wrote:
From: Pali Rohár <[email protected]>
SoC Control 1 Register (offset 0x18204) is already defined by macro
SOC_CONTROL_REG1.
Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c
code and remove the other definition.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Thanks,
Stefan
---
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 4 ++--
arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 4 ----
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
index adef3331a7..717bcfb29c 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
@@ -49,7 +49,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8
count)
reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
}
- tmp = reg_read(SOC_CTRL_REG);
+ tmp = reg_read(SOC_CONTROL_REG1);
tmp &= ~0x03;
for (idx = 0; idx < count; idx++) {
@@ -79,7 +79,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8
count)
}
}
- reg_write(SOC_CTRL_REG, tmp);
+ reg_write(SOC_CONTROL_REG1, tmp);
/* Support gen1/gen2 */
DEBUG_INIT_FULL_S("Support gen1/gen2\n");
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 3f30b6bf97..a882d24208 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -14,10 +14,6 @@
/* PCI Express Control and Status Registers */
#define MAX_PEX_BUSSES 256
-#define MISC_REGS_OFFSET 0x18200
-#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
-#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
-
#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
(0x40000 + ((if) - 1) * 0x4000) : \
0x80000)
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: [email protected]
