Re: [PATCH u-boot-marvell 9/9] arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines

[Stefan Roese]

On 24.09.21 22:59, Marek Behún wrote:

From: Pali Rohár <p...@kernel.org>

These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.

Signed-off-by: Pali Rohár <p...@kernel.org>
Reviewed-by: Marek Behún <marek.be...@nic.cz>

Reviewed-by: Stefan Roese <s...@denx.de>

Thanks,
Stefan

---
  arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h 
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 55a4c267c4..64193d5288 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -12,7 +12,7 @@
  /* Direct access to PEX0 Root Port's PCIe Capability structure */
  #define PEX0_RP_PCIE_CFG_OFFSET               (0x00080000 + 0x60)

-/* PEX_CAPABILITIES_REG fields */

+/* SOC_CONTROL_REG1 fields */
  #define PCIE0_ENABLE_OFFS             0
  #define PCIE0_ENABLE_MASK             (0x1 << PCIE0_ENABLE_OFFS)
  #define PCIE1_ENABLE_OFFS             1

Viele Grüße,
Stefan

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