> From: U-Boot <u-boot-boun...@lists.denx.de> On Behalf Of Chia-Wei Wang > Sent: Friday, October 15, 2021 10:04 AM > > ACRY is deisnged to accerlerate ECC/RSA digital signature generation and > verification. > > Signed-off-by: Chia-Wei Wang <chiawei_w...@aspeedtech.com> > --- > drivers/crypto/aspeed/Kconfig | 10 ++ > drivers/crypto/aspeed/Makefile | 1 + > drivers/crypto/aspeed/aspeed_acry.c | 182 > ++++++++++++++++++++++++++++ > lib/rsa/Kconfig | 10 +- > 4 files changed, 202 insertions(+), 1 deletion(-) create mode 100644 > drivers/crypto/aspeed/aspeed_acry.c > > diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig > index 471c06f986..9bf317177a 100644 > --- a/drivers/crypto/aspeed/Kconfig > +++ b/drivers/crypto/aspeed/Kconfig > @@ -8,3 +8,13 @@ config ASPEED_HACE > Enabling this allows the use of SHA operations in hardware without > requiring the SHA software implementations. It also improves > performance > and saves code size. > + > +config ASPEED_ACRY > + bool "ASPEED RSA and ECC Engine" > + depends on ASPEED_AST2600 > + help > + Select this option to enable a driver for using the RSA/ECC engine in > + the ASPEED BMC SoCs. > + > + Enabling this allows the use of RSA/ECC operations in hardware without > requiring the > + software implementations. It also improves performance and saves code > size. > diff --git a/drivers/crypto/aspeed/Makefile b/drivers/crypto/aspeed/Makefile > index 84e6bfe82a..58b55fc46e 100644 > --- a/drivers/crypto/aspeed/Makefile > +++ b/drivers/crypto/aspeed/Makefile > @@ -1 +1,2 @@ > obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o > +obj-$(CONFIG_ASPEED_ACRY) += aspeed_acry.o > diff --git a/drivers/crypto/aspeed/aspeed_acry.c > b/drivers/crypto/aspeed/aspeed_acry.c > new file mode 100644 > index 0000000000..0b948f828a > --- /dev/null > +++ b/drivers/crypto/aspeed/aspeed_acry.c > @@ -0,0 +1,182 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright 2021 ASPEED Technology Inc. > + */ > +#include <config.h> > +#include <common.h> > +#include <clk.h> > +#include <dm.h> > +#include <asm/types.h> > +#include <asm/io.h> > +#include <dm/device.h> > +#include <dm/fdtaddr.h> > +#include <linux/delay.h> > +#include <u-boot/rsa-mod-exp.h> > + > +/* ACRY register offsets */ > +#define ACRY_CTRL1 0x00 > +#define ACRY_CTRL1_RSA_DMA BIT(1) > +#define ACRY_CTRL1_RSA_START BIT(0) > +#define ACRY_CTRL2 0x44 > +#define ACRY_CTRL3 0x48 > +#define ACRY_CTRL3_SRAM_AHB_ACCESS BIT(8) > +#define ACRY_CTRL3_ECC_RSA_MODE_MASK GENMASK(5, 4) > +#define ACRY_CTRL3_ECC_RSA_MODE_SHIFT 4 > +#define ACRY_DMA_DRAM_SADDR 0x4c > +#define ACRY_DMA_DMEM_TADDR 0x50 > +#define ACRY_DMA_DMEM_TADDR_LEN_MASK GENMASK(15, 0) > +#define ACRY_DMA_DMEM_TADDR_LEN_SHIFT 0 > +#define ACRY_RSA_PARAM 0x58 > +#define ACRY_RSA_PARAM_EXP_MASK GENMASK(31, 16) > +#define ACRY_RSA_PARAM_EXP_SHIFT 16 > +#define ACRY_RSA_PARAM_MOD_MASK GENMASK(15, 0) > +#define ACRY_RSA_PARAM_MOD_SHIFT 0 > +#define ACRY_RSA_INT_EN 0x3f8 > +#define ACRY_RSA_INT_EN_RSA_READY BIT(2) > +#define ACRY_RSA_INT_EN_RSA_CMPLT BIT(1) > +#define ACRY_RSA_INT_STS 0x3fc > +#define ACRY_RSA_INT_STS_RSA_READY BIT(2) > +#define ACRY_RSA_INT_STS_RSA_CMPLT BIT(1) > + > +/* misc. constant */ > +#define ACRY_ECC_MODE 2 > +#define ACRY_RSA_MODE 3 > +#define ACRY_CTX_BUFSZ 0x600 > + > +struct aspeed_acry { > + phys_addr_t base; > + phys_addr_t sram_base; /* internal sram */ > + struct clk clk; > +}; > + > +static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, > uint32_t sig_len, > + struct key_prop *prop, uint8_t *out) { > + int i, j; > + u8 *ctx; > + u8 *ptr; > + u32 reg; > + struct aspeed_acry *acry = dev_get_priv(dev); > + > + ctx = memalign(16, ACRY_CTX_BUFSZ); > + if (!ctx) > + return -ENOMEM; > + > + memset(ctx, 0, ACRY_CTX_BUFSZ); > + > + ptr = (u8 *)prop->public_exponent; > + for (i = prop->exp_len - 1, j = 0; i >= 0; --i) { > + ctx[j] = ptr[i]; > + j++; > + j = (j % 16) ? j : j + 32; > + } > + > + ptr = (u8 *)prop->modulus; > + for (i = (prop->num_bits >> 3) - 1, j = 0; i >= 0; --i) { > + ctx[j + 16] = ptr[i]; > + j++; > + j = (j % 16) ? j : j + 32; > + } > + > + ptr = (u8 *)sig; > + for (i = sig_len - 1, j = 0; i >= 0; --i) { > + ctx[j + 32] = ptr[i]; > + j++; > + j = (j % 16) ? j : j + 32; > + } > + > + writel((u32)ctx, acry->base + ACRY_DMA_DRAM_SADDR); > + > + reg = (((prop->exp_len << 3) << ACRY_RSA_PARAM_EXP_SHIFT) & > ACRY_RSA_PARAM_EXP_MASK) | > + ((prop->num_bits << ACRY_RSA_PARAM_MOD_SHIFT) & > ACRY_RSA_PARAM_MOD_MASK); > + writel(reg, acry->base + ACRY_RSA_PARAM); > + > + reg = (ACRY_CTX_BUFSZ << ACRY_DMA_DMEM_TADDR_LEN_SHIFT) & > ACRY_DMA_DMEM_TADDR_LEN_MASK; > + writel(reg, acry->base + ACRY_DMA_DMEM_TADDR); > + > + reg = (ACRY_RSA_MODE << ACRY_CTRL3_ECC_RSA_MODE_SHIFT) & > ACRY_CTRL3_ECC_RSA_MODE_MASK; > + writel(reg, acry->base + ACRY_CTRL3); > + > + writel(ACRY_CTRL1_RSA_DMA | ACRY_CTRL1_RSA_START, acry->base + > +ACRY_CTRL1); > + > + /* polling RSA status */ > + while (1) { > + reg = readl(acry->base + ACRY_RSA_INT_STS); > + if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & > ACRY_RSA_INT_STS_RSA_CMPLT)) > + break;
Interrupt status clear is missed here. Will prepare v7 patch to fix this. Regards, Chiawei