[PATCH v3 12/12] mmc: fsl_esdhc_imx: set sysctl register for clock initialization

[Sean Anderson]

[ fsl_esdhc commit 263ddfc3454ead3a988adef39b962479adce2b28 ]

The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.

Signed-off-by: Yangbo Lu <yangbo...@nxp.com>
Signed-off-by: Sean Anderson <sean.ander...@seco.com>
---

(no changes since v1)

 drivers/mmc/fsl_esdhc_imx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 25e912ba95..9299635f50 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1020,7 +1020,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, 
struct mmc *mmc)
                esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
        /* Set the initial clock speed */
-       mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
+       set_sysctl(priv, mmc, 400000);
 
        /* Disable the BRR and BWR bits in IRQSTAT */
        esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
-- 
2.25.1