The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessan...@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-...@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhi...@leica-geosystems.com>
Cc: Fabio Estevam <feste...@gmail.com>
Cc: Joe Hershberger <joe.hershber...@ni.com>
Cc: Lukasz Majewski <lu...@denx.de>
Cc: Marcel Ziswiler <marcel.ziswi...@toradex.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Michael Trimarchi <mich...@amarulasolutions.com>
Cc: Peng Fan <peng....@nxp.com>
Cc: Ramon Fried <rfried....@gmail.com>
Cc: Sean Anderson <sean...@gmail.com>
Cc: Stefano Babic <sba...@denx.de>
Cc: Tim Harvey <thar...@gateworks.com>
Cc: Tommaso Merciai <tommaso.merc...@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
V3: New patch
---
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 51 +------------------
.../dh_imx8mp/imx8mp_dhcom_pdk2.c | 12 -----
board/engicam/imx8mm/icore_mx8mm.c | 15 +-----
board/kontron/pitx_imx8m/pitx_imx8m.c | 14 +----
4 files changed, 3 insertions(+), 89 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 3f03b515a63..51ebc27244d 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -868,55 +868,7 @@ static int imx8mp_eqos_interface_init(struct udevice *dev,
}
#endif
-#ifdef CONFIG_FEC_MXC
-int set_clk_enet(enum enet_freq type)
-{
- u32 target;
- u32 enet1_ref;
-
- switch (type) {
- case ENET_125MHZ:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
- break;
- case ENET_50MHZ:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
- break;
- case ENET_25MHZ:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
- break;
- default:
- return -EINVAL;
- }
-
- /* disable the clock first */
- clock_enable(CCGR_ENET1, 0);
- clock_enable(CCGR_SIM_ENET, 0);
-
- /* set enet axi clock 266Mhz */
- target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET_AXI_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | enet1_ref |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET_REF_CLK_ROOT, target);
-
- target = CLK_ROOT_ON |
- ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
-
- /* enable clock */
- clock_enable(CCGR_SIM_ENET, 1);
- clock_enable(CCGR_ENET1, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_IMX8MP
+#if defined(CONFIG_IMX8MP) && defined(CONFIG_FEC_MXC)
static int imx8mp_fec_interface_init(struct udevice *dev,
phy_interface_t interface_type,
bool mx8mp)
@@ -948,7 +900,6 @@ static int imx8mp_fec_interface_init(struct udevice *dev,
return 0;
}
#endif
-#endif
int board_interface_eth_init(struct udevice *dev, phy_interface_t
interface_type)
{
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index cb9973900bd..5edb85e1de5 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -37,17 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
-static void setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Enable RGMII TX clk output. */
- setbits_le32(&gpr->gpr[1], BIT(22));
-
- set_clk_enet(ENET_125MHZ);
-}
-
static int dh_imx8_setup_ethaddr(void)
{
unsigned char enetaddr[6];
@@ -114,7 +103,6 @@ int dh_setup_mac_address(void)
int board_init(void)
{
- setup_fec();
return 0;
}
diff --git a/board/engicam/imx8mm/icore_mx8mm.c
b/board/engicam/imx8mm/icore_mx8mm.c
index 4f7c699d7d1..320388faae3 100644
--- a/board/engicam/imx8mm/icore_mx8mm.c
+++ b/board/engicam/imx8mm/icore_mx8mm.c
@@ -29,7 +29,7 @@ static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-static void setup_iomux_fec(void)
+static void setup_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
@@ -40,19 +40,6 @@ static void setup_iomux_fec(void)
gpio_direction_output(FEC_RST_PAD, 1);
}
-static int setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- setup_iomux_fec();
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], 13, 0);
-
- return set_clk_enet(ENET_125MHZ);
-}
-
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c
b/board/kontron/pitx_imx8m/pitx_imx8m.c
index af1832c4736..fcda86bc1b1 100644
--- a/board/kontron/pitx_imx8m/pitx_imx8m.c
+++ b/board/kontron/pitx_imx8m/pitx_imx8m.c
@@ -92,24 +92,12 @@ static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-static void setup_iomux_fec(void)
+static void setup_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
}
-static int setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- setup_iomux_fec();
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
- return set_clk_enet(ENET_125MHZ);
-}
-
int board_phy_config(struct phy_device *phydev)
{
unsigned int val;
--
2.39.1
