The driver currently only waits for DMA_MODE SWR bit to clear itself. This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset before IOMUX GPR[1] content is latched into the MAC and used. Without the proper reset, the i.MX8M Plus MAC variant does not take the value in IOMUX GPR[1] into account, which makes it impossible e.g. to switch interface mode from RGMII to any other.
Since proper reset is desired in general to put the block into defined state, always assert the DMA_MODE SWR bit before waiting for the bit to clear itself. Reviewed-by: Ramon Fried <[email protected]> Signed-off-by: Marek Vasut <[email protected]> --- Cc: "Ariel D'Alessandro" <[email protected]> Cc: "NXP i.MX U-Boot Team" <[email protected]> Cc: Andrey Zhizhikin <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Joe Hershberger <[email protected]> Cc: Lukasz Majewski <[email protected]> Cc: Marcel Ziswiler <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Michael Trimarchi <[email protected]> Cc: Peng Fan <[email protected]> Cc: Ramon Fried <[email protected]> Cc: Sean Anderson <[email protected]> Cc: Stefano Babic <[email protected]> Cc: Tim Harvey <[email protected]> Cc: Tommaso Merciai <[email protected]> Cc: [email protected] --- V2: Add RB from Ramon V3: No change --- drivers/net/dwc_eth_qos.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9a5575e7b83..ec58697b311 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev) eqos->reg_access_ok = true; + /* + * Assert the SWR first, the actually reset the MAC and to latch in + * e.g. i.MX8M Plus GPR[1] content, which selects interface mode. + */ + setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR); + ret = wait_for_bit_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR, false, eqos->config->swr_wait, false); -- 2.39.1
