Hi Pali, I've created a pull request for this patch to the Marvell repo.
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/41 Thanks, Tony On Thu, Apr 13, 2023 at 11:06 PM Stefan Roese <[email protected]> wrote: > > On 4/3/23 06:42, Tony Dinh wrote: > > - DDR Training sequence happens very fast. The speedup in boot time is > > negligible by skipping the training sequence during 2nd boot or after. > > So remove the check and skip. > > - This change improves the robustness of DDR training. If u-boot crashed > > during DDR training, the training could be left in a limbo state, where > > the BootROM has recorded that it is already in a 2nd boot. The training > > must be repeated in this scenario to get out of this limbo state, but due > > to the check it cannot be performed. > > > > Signed-off-by: Tony Dinh <[email protected]> > > Applied to u-boot-marvell/master > > Thanks, > Stefan > > > --- > > > > drivers/ddr/marvell/a38x/mv_ddr_plat.c | 7 ------- > > 1 file changed, 7 deletions(-) > > > > diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c > > b/drivers/ddr/marvell/a38x/mv_ddr_plat.c > > index 6e7949ac72..8ec9fb0874 100644 > > --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c > > +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c > > @@ -1363,13 +1363,6 @@ int mv_ddr_pre_training_soc_config(const char > > *ddr_type) > > DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS); > > } > > > > - /* Check if DRAM is already initialized */ > > - if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & > > - (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { > > - printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); > > - return MV_OK; > > - } > > - > > /* Fix read ready phases for all SOC in reg 0x15c8 */ > > reg_val = reg_read(TRAINING_DBG_3_REG); > > > > Viele Grüße, > Stefan Roese > > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: [email protected]
