On Feb 7, 2011, at 3:14 PM, <haiying.w...@freescale.com> <haiying.w...@freescale.com> wrote:
> From: Haiying Wang <haiying.w...@freescale.com> > > P1021 has some QE pins which need to be set in pmuxcr register before using QE > functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth > mode. > QE9 and QE12 are set for MII management. QE12 needs to be released after MII > access because QE12 pin is muxed with LBCTL signal. > > P1021MDS has to load the microcode from NAND flash, this patchs add support to > load ucode from NAND before initializing qe. > > Signed-off-by: Haiying Wang <haiying.w...@freescale.com> > --- > v2: remove misc_init_r, make changes based on laste commits in u-boot-85xx.git > arch/powerpc/cpu/mpc85xx/speed.c | 4 ++ > arch/powerpc/include/asm/immap_85xx.h | 13 ++++++++ > board/freescale/p1021mds/p1021mds.c | 51 +++++++++++++++++++++++++++++++++ > drivers/qe/uec.c | 40 +++++++++++++++++++++++++- > include/configs/P1021MDS.h | 44 ++++++++++++++++++++++++++++ > 5 files changed, 151 insertions(+), 1 deletions(-) Can we split this patch up into the QE parts for P1021 and the board parts for P1021MDS > > diff --git a/arch/powerpc/cpu/mpc85xx/speed.c > b/arch/powerpc/cpu/mpc85xx/speed.c > index f2aa8d0..ae94ee8 100644 > --- a/arch/powerpc/cpu/mpc85xx/speed.c > +++ b/arch/powerpc/cpu/mpc85xx/speed.c > @@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo) > #endif > > #ifdef CONFIG_QE > +#ifdef CONFIG_P1021 > + sysInfo->freqQE = sysInfo->freqSystemBus; > +#else > qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) > >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; > sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; > #endif > +#endif > > #if defined(CONFIG_FSL_LBC) > #if defined(CONFIG_SYS_LBC_LCRR) > diff --git a/arch/powerpc/include/asm/immap_85xx.h > b/arch/powerpc/include/asm/immap_85xx.h > index 99ecb83..d0fa79b 100644 > --- a/arch/powerpc/include/asm/immap_85xx.h > +++ b/arch/powerpc/include/asm/immap_85xx.h > @@ -1909,6 +1909,19 @@ typedef struct ccsr_gur { > #define MPC85xx_PMUXCR_SD_DATA 0x80000000 > #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 > #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 > +#define MPC85xx_PMUXCR_QE0 0x00008000 > +#define MPC85xx_PMUXCR_QE1 0x00004000 > +#define MPC85xx_PMUXCR_QE2 0x00002000 > +#define MPC85xx_PMUXCR_QE3 0x00001000 > +#define MPC85xx_PMUXCR_QE4 0x00000800 > +#define MPC85xx_PMUXCR_QE5 0x00000400 > +#define MPC85xx_PMUXCR_QE6 0x00000200 > +#define MPC85xx_PMUXCR_QE7 0x00000100 > +#define MPC85xx_PMUXCR_QE8 0x00000080 > +#define MPC85xx_PMUXCR_QE9 0x00000040 > +#define MPC85xx_PMUXCR_QE10 0x00000020 > +#define MPC85xx_PMUXCR_QE11 0x00000010 > +#define MPC85xx_PMUXCR_QE12 0x00000008 > u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ > u8 res6[8]; > u32 devdisr; /* Device disable control */ > diff --git a/board/freescale/p1021mds/p1021mds.c > b/board/freescale/p1021mds/p1021mds.c > index 2dfcf13..29972f8 100644 > --- a/board/freescale/p1021mds/p1021mds.c > +++ b/board/freescale/p1021mds/p1021mds.c > @@ -37,6 +37,45 @@ > #include <tsec.h> > #include <netdev.h> > > +#ifdef CONFIG_QE > +const qe_iop_conf_t qe_iop_conf_tab[] = { > + /* QE_MUX_MDC */ > + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ > + /* QE_MUX_MDIO */ > + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ > + > + /* UCC_1_MII */ > + {0, 23, 2, 0, 2}, /* CLK12 */ > + {0, 24, 2, 0, 1}, /* CLK9 */ > + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ > + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ > + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ > + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ > + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ > + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ > + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ > + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ > + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ > + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ > + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ > + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ > + {0, 17, 2, 0, 2}, /* ENET1_CRS */ > + {0, 16, 2, 0, 2}, /* ENET1_COL */ > + > + /* UCC_5_RMII */ > + {1, 11, 2, 0, 1}, /* CLK13 */ > + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ > + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ > + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ > + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ > + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ > + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ > + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ > + > + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ > +}; > +#endif > + > int board_early_init_f(void) > { > > @@ -100,6 +139,14 @@ int board_eth_init(bd_t *bis) > > tsec_eth_init(bis, tsec_info, num); > > +#if defined(CONFIG_UEC_ETH) > + /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); > + > + uec_standard_init(bis); > +#endif > + > return pci_eth_init(bis); > } > #endif > @@ -119,5 +166,9 @@ void ft_board_setup(void *blob, bd_t *bd) > > FT_FSL_PCI_SETUP; > > +#ifdef CONFIG_QE > + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", > + sizeof("okay"), 0); > +#endif > } > #endif > diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c > index 282ab23..04d7987 100644 > --- a/drivers/qe/uec.c > +++ b/drivers/qe/uec.c > @@ -1,5 +1,5 @@ > /* > - * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. > + * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. > * > * Dave Liu <dave...@freescale.com> > * > @@ -30,6 +30,9 @@ > #include "uec.h" > #include "uec_phy.h" > #include "miiphy.h" > +#ifdef CONFIG_P1021 > +#define BCSR11_ENET_MICRST 0x20 > +#endif > > /* Default UTBIPAR SMI address */ > #ifndef CONFIG_UTBIPAR_INIT_TBIPA > @@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev) > { > uec_private_t *uec = (uec_private_t *)dev->priv; > > +#ifdef CONFIG_P1021 > + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); > + > + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); > +#endif > + > /* Update the link, speed, duplex */ > uec->mii_info->phyinfo->read_status(uec->mii_info); > > +#ifdef CONFIG_P1021 > + /* > + * QE12 is muxed with LBCTL, it needs to be released for enabling > + * LBCTL signal for LBC usage. > + */ > + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); > +#endif > + > /* Adjust the interface according to speed */ > adjust_link(dev); > } > @@ -1198,10 +1217,24 @@ static int uec_init(struct eth_device* dev, bd_t *bd) > uec_private_t *uec; > int err, i; > struct phy_info *curphy; > +#ifdef CONFIG_P1021 > + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); > +#endif > > uec = (uec_private_t *)dev->priv; > > if (uec->the_first_run == 0) { > +#ifdef CONFIG_P1021 > + /* reset micrel phy for each UEC */ > + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); > + udelay(200); > + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); > + Hmm, this is board specific, can we not do this in board_*_f or _r? > + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); > +#endif > + > err = init_phy(dev); > if (err) { > printf("%s: Cannot initialize PHY, aborting.\n", > @@ -1228,6 +1261,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd) > udelay(100000); > } while (1); > > +#ifdef CONFIG_P1021 > + /* QE12 needs to be released for enabling LBCTL signal*/ > + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); > +#endif > + > if (err || i <= 0) > printf("warning: %s: timeout on PHY link\n", dev->name); - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot