Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10.
This option allows to change the bitstream on the filesystem and apply
changes with warm reboot without the need for a power cycle.

Signed-off-by: Michał Barnaś <bar...@google.com>
---

 arch/arm/mach-socfpga/Kconfig   | 8 ++++++++
 arch/arm/mach-socfpga/spl_a10.c | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 114d243812..89303f1f16 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -80,6 +80,14 @@ config TARGET_SOCFPGA_ARRIA10
        imply FPGA_SOCFPGA
        imply SPL_USE_TINY_PRINTF
 
+config TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
+       bool "Always reprogram Arria 10 FPGA"
+       depends on TARGET_SOCFPGA_ARRIA10
+       help
+         Arria 10 FPGA is only programmed during the cold boot.
+         This option forces the FPGA to be reprogrammed every reboot,
+         allowing to change the bitstream and apply it with warm reboot.
+
 config TARGET_SOCFPGA_CYCLONE5
        bool
        select TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 9edbbf4a29..d5d3327a42 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -122,7 +122,11 @@ void spl_board_init(void)
        arch_early_init_r();
 
        /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
+       if (is_regular_boot_valid()) {
+#else
        if (is_fpgamgr_user_mode()) {
+#endif
                ret = config_pins(gd->fdt_blob, "shared");
                if (ret)
                        return;
@@ -130,7 +134,11 @@ void spl_board_init(void)
                ret = config_pins(gd->fdt_blob, "fpga");
                if (ret)
                        return;
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
+       } else {
+#else
        } else if (!is_fpgamgr_early_user_mode()) {
+#endif
                /* Program IOSSM(early IO release) or full FPGA */
                fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 
-- 
2.44.0.rc1.240.g4c46232300-goog

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