Historically, PLLD2 mirrored PLLD's layout on Tegra30 and 114. However,
with the introduction of Tegra124, this changed. This layout alteration was
not considered, and it now requires a corrective action to prevent future
complications.

Signed-off-by: Svyatoslav Ryhel <[email protected]>
---
 arch/arm/mach-tegra/tegra124/clock.c | 4 ++--
 arch/arm/mach-tegra/tegra210/clock.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra124/clock.c 
b/arch/arm/mach-tegra/tegra124/clock.c
index 0ea212f80e2..8a6735d71af 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -598,8 +598,8 @@ struct clk_pll_info 
tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
          .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, 
.kvco_shift = 0, .kvco_mask = 1 },     /* PLLE */
        { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift 
= 20, .p_mask = 0x07,
          .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, 
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
-       { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift 
= 20, .p_mask = 0x07,
-         .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, 
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
+       { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift 
= 20, .p_mask = 0xF,
+         .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, 
.kvco_shift = 24, .kvco_mask = 1 },   /* PLLD2 */
        { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift 
= 20,  .p_mask = 0xF,
          .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, 
.kvco_shift = 24, .kvco_mask = 1 },   /* PLLDP */
 };
diff --git a/arch/arm/mach-tegra/tegra210/clock.c 
b/arch/arm/mach-tegra/tegra210/clock.c
index 04708f97144..d1ede5238dd 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -668,8 +668,8 @@ struct clk_pll_info 
tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
          .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, 
.kvco_shift = 0, .kvco_mask = 1 },     /* PLLE */
        { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, 
.p_mask = 0,
          .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, 
.kvco_shift = 0, .kvco_mask = 0 },       /* PLLS (gone)*/
-       { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift 
= 20, .p_mask = 0x07,
-         .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, 
.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
+       { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift 
= 19, .p_mask = 0x1F,
+         .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, 
.kvco_shift = 24, .kvco_mask = 1 },   /* PLLD2 */
        { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift 
= 19,  .p_mask = 0x1F,
          .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, 
.kvco_shift = 24, .kvco_mask = 1 },   /* PLLDP */
 };
-- 
2.43.0

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