[PATCH v1 3/5] arm: dts: agilex5: Update CCU configuration

[tingting . meng]

From: Tingting Meng <tingting.m...@altera.com>

Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.

Signed-off-by: Tingting Meng <tingting.m...@altera.com>
---
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi 
b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 8d6503dd091..dd6cb558f82 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -208,7 +208,8 @@
                                intel,offset-settings =
                                        /* DMIUSMCTCR */
                                        <0x00000300 0x00000001 0x00000003>,
-                                       <0x00000300 0x00000003 0x00000003>;
+                                       <0x00000300 0x00000003 0x00000003>,
+                                       <0x00000308 0x00000004 0x0000001F>;
                                bootph-all;
                        };
 
@@ -218,7 +219,8 @@
                                intel,offset-settings =
                                        /* DMIUSMCTCR */
                                        <0x00000300 0x00000001 0x00000003>,
-                                       <0x00000300 0x00000003 0x00000003>;
+                                       <0x00000300 0x00000003 0x00000003>,
+                                       <0x00000308 0x00000004 0x0000001F>;
                                bootph-all;
                        };
                };
-- 
2.25.1