Hi, I am manually adding Michael, as apparently he was not listed automatically.
On 09/09/2025 at 12:12:26 +02, Miquel Raynal <[email protected]> wrote: > Hello, > > On 03/07/2025 at 19:02:53 +02, Miquel Raynal <[email protected]> > wrote: > >> All these chips are dual and quad capable. They are also DTR capable, >> but the core is not yet ready for that. >> >> Performances of all chips are comparable at 30MHz and are as follow: >> Eraseblock single read speed: 938kiB/s >> Eraseblock dual read speed: 1068kiB/s >> Eraseblock quad read speed: 3751kiB/s >> >> Signed-off-by: Miquel Raynal <[email protected]> > > I believe this patch has been out for more than 2 months and is simple > enough, any plans for taking it soon? It's now been few more months and I haven't been notified this patch got merged. It is also not visible in upstream U-Boot. Could we please speed up the merging process, especially for such simple change? Thanks, Miquèl
