On Thu, Nov 13, 2025 at 10:50:34AM +0100, Miquel Raynal wrote: > Hi, > > I am manually adding Michael, as apparently he was not listed > automatically. > > On 09/09/2025 at 12:12:26 +02, Miquel Raynal <[email protected]> > wrote: > > > Hello, > > > > On 03/07/2025 at 19:02:53 +02, Miquel Raynal <[email protected]> > > wrote: > > > >> All these chips are dual and quad capable. They are also DTR capable, > >> but the core is not yet ready for that. > >> > >> Performances of all chips are comparable at 30MHz and are as follow: > >> Eraseblock single read speed: 938kiB/s > >> Eraseblock dual read speed: 1068kiB/s > >> Eraseblock quad read speed: 3751kiB/s > >> > >> Signed-off-by: Miquel Raynal <[email protected]> > > > > I believe this patch has been out for more than 2 months and is simple > > enough, any plans for taking it soon? > > It's now been few more months and I haven't been notified this patch got > merged. It is also not visible in upstream U-Boot. Could we please speed > up the merging process, especially for such simple change?
Jagan, Michael, Dario, do you need some help with the mtd/spi related patches? This hass been going on for some time. Thanks! -- Tom
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