Add a 100 ms delay after clearing the core soft reset bit to ensure the DWC3 controller has sufficient time to complete its reset sequence before subsequent register accesses.
Without this delay, USB initialization can fail on some Qualcomm platforms, particularly when using super-speed capable PHYs like the QMP USB3-DP Combo PHY on SC7280/QCM6490. The change is taken from following upstream Linux implementation: https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/usb/dwc3/core.c?id=f88359e1588b85cf0e8209ab7d6620085f3441d9 Signed-off-by: Balaji Selvanathan <[email protected]> --- v2: - Gave correct commit id for linux implementation --- drivers/usb/dwc3/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 847fa1f82c3..ff0bca0dd8e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -94,6 +94,8 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) reg &= ~DWC3_GCTL_CORESOFTRESET; dwc3_writel(dwc->regs, DWC3_GCTL, reg); + mdelay(100); + return 0; } -- 2.34.1
