From: Alif Zakuan Yuslaimi <[email protected]> This patch set updates the boot support for the Altera SoCFPGA Gen5/Arria10 platform in U-Boot. The changes include: 1. Update MMU/dcache setup across Gen5/Arria10 using common driver 2. Add ECC scrubbing support for Gen5/Arria10 3. Add DRAM size checking for Gen5/Arria10 4. Assign unit address to memory node in common SoCFPGA device tree file
This patch set has been tested on CycloneV devkit with SDMMC boot and RAM boot (TFTP & ARM DS debugger). Tested on Arria10 devkit with RAM boot as well Alif Zakuan Yuslaimi (5): arm: socfpga: Consolidate dram_bank_mmu_setup() ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10 ddr: altera: gen5: Add DRAM size checking ddr: altera: arria10: Add DRAM size checking arch: arm: socfpga: Assign unit address to memory node arch/arm/dts/socfpga-common-u-boot.dtsi | 2 +- arch/arm/dts/socfpga_arria5_secu1.dts | 2 +- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 2 +- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 2 +- .../dts/socfpga_cyclone5_de10_standard.dts | 2 +- arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 2 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- arch/arm/mach-socfpga/Kconfig | 1 + arch/arm/mach-socfpga/misc.c | 31 ++++++++ arch/arm/mach-socfpga/misc_arria10.c | 26 ------- arch/arm/mach-socfpga/spl_gen5.c | 4 + drivers/ddr/altera/Makefile | 4 +- drivers/ddr/altera/sdram_arria10.c | 57 +++++++++----- drivers/ddr/altera/sdram_gen5.c | 38 +++++++++- drivers/ddr/altera/sdram_soc32.c | 74 +++++++++++++++++++ drivers/ddr/altera/sdram_soc32.h | 11 +++ 16 files changed, 205 insertions(+), 55 deletions(-) create mode 100644 drivers/ddr/altera/sdram_soc32.c create mode 100644 drivers/ddr/altera/sdram_soc32.h -- 2.43.7
